IN74HC174AD Integral Corp., IN74HC174AD Datasheet

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IN74HC174AD

Manufacturer Part Number
IN74HC174AD
Description
Manufacturer
Integral Corp.
Datasheet
Hex D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS
device inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LS/ALSTTL outputs.
Reset inputs. Each flip-flop is loaded with a low-to-high transition of
the Clock input. Reset is asynchronous and active-low.
The IN74HC174A is identical in pinout to the LS/ALS174. The
This device consists of six D flip-flops with common Clock and
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
INTEGRAL
LOGIC DIAGRAM
PIN 8 = GND
PIN 16=V
CC
X = Don’t care
L = LOW voltage level
H = HIGH voltage level
Reset
H
H
H
H
L
T
A
FUNCTION TABLE
ORDERING INFORMATION
= -55 to 125 C for all packages
Inputs
PIN ASSIGNMENT
Clock
IN74HC174AN Plastic
IN74HC174AD SOIC
X
L
IZ74HC174A Chip
TECHNICAL DATA
IN74HC174A
D
X
H
X
X
L
no change
no change
Output
Q
H
L
L
1

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IN74HC174AD Summary of contents

Page 1

... Operating Voltage Range: 2.0 to 6.0 V Low Input Current: 1.0 A High Noise Immunity Characteristic of CMOS Devices LOGIC DIAGRAM PIN 16=V CC PIN 8 = GND INTEGRAL TECHNICAL DATA IN74HC174A ORDERING INFORMATION IN74HC174AN Plastic IN74HC174AD SOIC IZ74HC174A Chip T = -55 to 125 C for all packages A PIN ASSIGNMENT FUNCTION TABLE Inputs Output Reset Clock D ...

Page 2

MAXIMUM RATINGS Symbol V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) OUT I DC Input Current, per Pin Output Current, per ...

Page 3

DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Minimum High-Level IH Input Voltage V Maximum Low -Level IL Input Voltage V Minimum High-Level OH Output Voltage V Maximum Low-Level OL Output Voltage I Maximum Input IN Leakage Current I Maximum Quiescent CC ...

Page 4

AC ELECTRICAL CHARACTERISTICS Symbol Parameter f Maximum Clock Frequency (50% Duty Cycle) max (Figures 1 and Maximum Propagation Delay, Clock to Q (Figures PLH PHL 1 and 4) t Maximum Propagation Delay , Reset to Q ...

Page 5

CLOCK 50% 10 1/f max t PLH Q 90% 50% 10% t TLH Figure 1. Switching Waveforms VALID DATA 50 CLOCK 50% Figure 3. Switching Waveforms INTEGRAL t f RESET V CC GND ...

Page 6

Chip marking Chip marking :15HC174 Location of marking (mm): left lower corner x = 0.110 0.870; right lower corner x = 0.240 0.900 Chip thickness: 0.46 0.02 mm PAD LOCATION Pad No Symbol 01 Reset 02 ...

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