IW4040BD Integral Corp., IW4040BD Datasheet

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IW4040BD

Manufacturer Part Number
IW4040BD
Description
Manufacturer
Integral Corp.
Datasheet
12-Stage Binary Ripple Counter
High-Voltage Silicon-Gate CMOS
master-slave flip-flops. The state of a counter advances one count on the
negative transition of each input pulse; a high level on the RESET line resets
the counter to its all zeros state. Schmitt trigger action on the input-pulse
line permits unlimited rise and fall times.
The IW4040B is ripple-carry binary counter. All counter stages are
Operating Voltage Range: 3.0 to 18 V
Maximum input current of 1 A at 18 V over full package-temperature
range; 100 nA at 18 V and 25 C
Noise margin (over full package temperature range):
INTEGRAL
CLOCK
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
RESET
LOGIC DIAGRAM
10
11
PIN 8 = GND
PIN 16 =V
CC
9
7
5
3
6
2
4
14
13
12
15
1
Q10
Q11
Q2
Q3
Q5
Q9
Q12
Q4
Q6
Q8
Q1
Q7
H= high level
L = low level
X=don’t care
Clock
X
Inputs
FUNCTION TABLE
16
PIN ASSIGNMENT
GND
Q6
Q5
Q7
Q4
Q3
Q2
Q12
IW4040BN Plastic DIP
IW4040BD SOIC
IZ4040B
ORDERING INFORMATION
TECHNICAL DATA
Reset
IW4040B
1
16
H
L
L
1
2
3
4
5
6
7
8
T
A
for all packages
= -55 to 125 C
All Outputs are low
Advance to next
1
chip
Output state
16
15
14
13
12
11
10
No change
9
Output
state
V CC
Q11
Q10
Q8
Q9
RESET
CLOCK
Q1
PLASTIC DIP
N SUFFIX
1

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IW4040BD Summary of contents

Page 1

... Q11 1 Clock Q12 H= high level L = low level CC X=don’t care TECHNICAL DATA IW4040B N SUFFIX PLASTIC DIP ORDERING INFORMATION IW4040BN Plastic DIP IW4040BD SOIC IZ4040B chip T = -55 to 125 C A for all packages PIN ASSIGNMENT V CC Q12 Q11 ...

Page 2

MAXIMUM RATINGS Symbol V DC Supply Voltage (Referenced to GND Input Voltage (Referenced to GND Output Voltage (Referenced to GND) OUT I DC Input Current, per Pin IN P Power Dissipation in Still ...

Page 3

DC ELECTRICAL CHARACTERISTICS Symbol Parameter V Minimum High-Level IH Input Voltage V Maximum Low -Level IL Input Voltage V Minimum High-Level OH Output Voltage V Maximum Low-Level OL Output Voltage I Maximum Input Leakage IN Current I Maximum Quiescent CC ...

Page 4

AC ELECTRICAL CHARACTERISTICS Symbol Parameter f Maximum Clock Frequency (Figure 1) max Maximum Propagation Delay, Clock to Q1 (Figure 1) PLH PHL Maximum Propagation Delay, Q PLH PHL t Maximum Propagation Delay, Reset to ...

Page 5

CLOCK RESET ANY Clock Reset Q10 Q11 Q12 CLOCK RESET INTEGRAL 50% t rem t w 50% t PHL 50% Figure 3. Switching Waveforms TIMING DIAGRAM ...

Page 6

INTEGRAL IW4040B 6 ...

Page 7

Chip marking 4040 (0, Location of marking (mm): left lower corner x=0.199, y=1.792. Chip thickness: 0.46 0.02 (0.35 0.02 ) mm. PAD LOCATION Pad No Symbol 01 Q12 ...

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