CX28229-14 Mindspeed Technologies, CX28229-14 Datasheet
CX28229-14
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CX28229-14 Summary of contents
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CX28224/5/9 Inverse Multiplexing for ATM (IMA) Family Data Sheet 28229-DSH-001-D March 2004 ...
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... Ordering Information Manufacturing Part Model Number Number CX28224 CX28224-14 CX28225 CX28225-14 CX28229 CX28229-14 Revision History Revision Level Date A Preliminary July 2001 B Preliminary September 2001 C Preliminary September 2001 D Preliminary April 2002 E Preliminary May 2002 F Preliminary September 2002 A Released January 2003 C Released August 2003 ...
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... DSL serial data streams without a frame sync pulse. Individual ports can be operated in a 'pass thru' mode without the IMA overhead. The CX28229 provides direct connection to 8 serial links or can be expanded port IMA using the PHY side UTOPIA bus and external TC devices such as the RS8228 ...
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... Mb/s) Internal memory Connects directly to the Mindspeed SARs for inexpensive CPE solutions CX28224 2 ports CX28225 4 ports CX28229 32 ports Memory expandable bytes via external bus independent groups (using external PHYs): Each group can have links. Supports IMA versions 1.0 and 1.1 ...
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... Source Loopback (UTOPIA-to-Serial Configuration Only 2-35 2.6 Far-End Line Loopback (Serial Configuration Only 2-36 2.7 Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.8 Reference Designs 2-37 3 IMA Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Common Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.1 T1/E1 Using Internal Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 3.1.1.1 Using IMA_SysClk as the Transmit Clock 3-4 3.1.1.2 Using IMA_RefClk as the Transmit Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.1.2 DSL/T1/E1 Using UTOPIA-to-UTOPIA Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 28229-DSH-001-D Mindspeed Technologies ™ v ...
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... ATM Cell Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.2.1 Cell Delineation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.2 Processing Non-Standard Traffic Using the CX28229 5-4 5.2.3 Cell Screening 5-6 5 ...
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... Interface Control Register 7-65 0x202—ATMINTFC (ATM-side Interface Control Register 7-65 0x203—OUTSTAT (Output Status Control Register 7-65 0x204—SUMPORT (Summary Port Interrupt Status Register 7-66 0x205—ENSUMPORT (Summary Port Interrupt Control Register 7-66 0x208—PART/VER (Part Number/Version Register 7-67 28229-DSH-001-D Mindspeed Technologies ™ vii ...
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... IMA Group 7-88 0x41F—IMA_GRP_1TO4_SEM (Group Table Control 7-88 0x51F—IMA_GRP_5TO8_SEM (Group Table Control II (CX28229 Only 7-89 0x61F—IMA_GRP_9TO12_SEM (Group Table Control III (CX28229 Only)). . . . . . . . . . . . . . . 7-90 0x71F—IMA_GRP_13TO16_SEM (Group Table Control IV (CX28229 Only)). . . . . . . . . . . . . . 7-91 IMA_TX_GRPn_RX_TEST_PATTERN (Transmit Group Rx Test Pattern 7-92 IMA_TX_GRPn_CTL (Transmit Group Control Register) ...
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... UTOPIA Interface Timing (ATM Layer 8-11 8.1.4 UTOPIA Interface Timing (PHY Layer 8-15 8.1.5 JTAG Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 8.1.6 One-second Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 8.2 Expansion Memory Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 8.3 Absolute Maximum Ratings 8-21 8.4 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 8.5 Mechanical Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23 A IMA Version 1.1 PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.3 Symbols and Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-1 A.4 Conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.5 IMA PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 28229-DSH-001-D Mindspeed Technologies ™ ix ...
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... A.5.1 Global Statement of Conformance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.5.2 Instructions for Completing the PICS Proforma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2 A.5.3 IMA Protocol Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 A.6 PICS Proforma References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-21 B Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-1 x Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... IMA Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Figure 2-3. CX28229 Pinout Diagram UTOPIA-to-UTOPIA (Top View 2-5 Figure 2-4. CX28229 Logic Diagram (UTOPIA-to-Serial 2-19 Figure 2-5. CX28229 UTOPIA-to-Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Figure 2-6. CX28229 Pinout Diagram, UTOPIA-to-Serial (Top View 2-21 Figure 2-7 ...
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... UTOPIA Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16 Figure 8-12. UTOPIA Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17 Figure 8-13. JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18 Figure 8-14. One-second Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19 Figure 8-15. Read/Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 Figure 8-16. CX28224/5/9 Mechanical Drawing (Bottom View 8-23 Figure 8-17. CX28224/5/9 Mechanical Drawing (Top and Side Views 8-24 xii Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... Table 2-2. UTOPIA-to-UTOPIA Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 Table 2-3. CX2822x Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 Table 2-4. CX28229 UTOPIA-to-Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 Table 2-5. CX28229 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 Table 2-6. Cell Delineation Configuration Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 Table 3-1 ...
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... Expansion Memory Port Read/Write Timing Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-20 Table 8-14. Absolute Maximum Ratings (General 8-21 Table 8-15. Absolute Maximum Ratings (CX28229/CX28225/CX28224 8-21 Table 8-16. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-22 Table A-1. Basic IMA Protocol (BIP) Definition Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 Table A-2 ...
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... Rx Block IMA Engine Tx Block IMA clocks 28229-DSH-001-D IMA Block 1 TC Counters OneSec Micro interface JTAG Mindspeed Technologies ™ TC Block cell processor Line interface 0 cell processor Line interface 1 cell processor Line interface 2 cell processor Line interface 3 cell processor Line interface 4 cell processor ...
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... M values), the bringing up of the IMA group, and the graceful addition/recovery and deletion of links to and from the group. For the CX28229, this function is performed in the host software. The software itself is available from Mindspeed. Mindspeed Technologies ™ ...
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... IMA protocol is defined to allow symmetric or asymmetric cell rate transfer over the IMA virtual link. It allows for smooth introduction of each link in the group. It also allows graceful handling of error conditions and removal of a link. This function is performed internally by the CX28229 1.544 Mb ...
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... Always at least 1 ICP cell per frame ATM ATM ATM ICP ATM IMA control Protocol Cell ICP n IFSN = n Mindspeed Technologies CX28224/5/9 Data Sheet Figure 1-3. It ATM ATM ATM This cell was in the previous frame ATM ...
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... Bit 7 Set to 1 for ICP cell Bits 6–5 Unused and set to 0 Bits 4–0 Logical ID for physical link range (0... 31) Cyclical counter 255 Indicates position of ICP cell within the IMA frame of size M cells. Range: (0... M – 1) Mindspeed Technologies Introduction to IMA Table 1-2 lists format of ™ ...
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... Bits 1–0 11: Reserved IMA Frame Length 00: M=32 01: M=64 10: M=128 11: M=256 Transmit Clock Information Bits 7–6 Unused, set to 00 Bit 5 Transmit Clock Mode (0: ITC mode, 1: CTC mode) Bits 4–0 Tx LID of the timing reference link (TRL)—Range Mindspeed Technologies CX28224/5/9 Data Sheet ™ 28229-DSH-001-D ...
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... Version 1.1 Bit 7 Set to 0 for IMA Filler cell Bits 6–0 Unused and set to 0 Set to 0x6A (as defined in ITU-T I.432) Bits 15-10 Reserved field for future use—default value is all zeros Bits 9-0 CRC-10 as defined in ITU-T Recommendation I.610 Mindspeed Technologies Introduction to IMA ™ ...
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... Chapter 3 and in the ATM standard on IMA. Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... IMA implementation to absorb a minimum differential delay between the links. Each port requires memory for every 27 delay (at E1 provides for 34.375 rates). The CX28229 provides 256K bytes of on-board memory for the buffering necessary to re-align the links within an IMA group ...
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... Mindspeed provides a complete IMA and device driver in ANSI C to simplify system development. This software has been field tested and can be ported to virtually all systems. This is also covered in chapter 3, the IMA engine and the CX28229TAP IMA Software Programming Guide. Table 1-5 pointer to the structure IMA_DEV ...
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... This is an application defined function that disables interrupts from the IMA hardware device. This is an application defined function that enables interrupts from the IMA hardware device. This is an application defined function that accepts asynchronous event CX28224/5/9 messages from the Mindspeed Technologies ™ Introduction to IMA CX28224/5/9 Group CX28224/5/9 Group ...
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... Introduction to IMA 1.2.1 Software Subsystems The internal architecture of the CX28229TAP software is composed of five logical subsystems: Configuration (CF), Diagnostics (DG), IMA Group (GRP), Failure Monitoring (FM), and Performance Monitoring (PM). The following sections summarize the interfaces of the CX28224/5/9 IMA software device driver important to point out that the CX28224/5/9 products can be configured to run in different operating environments ...
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... These performance parameters are gathered over programmable, predetermined accumulation periods. The CX28229TAP calculates these statistics over 15 minute intervals. The PM data is available to the application grouped in a structure encompassing one of the two accumulation sets: the current 15 minute interval or the previous 15 minute interval. ...
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... Introduction to IMA 1-14 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... CX28229 256 Kbytes FOOTNOTE: (1) Internal memory is disabled when the external bus is used. (2) Normally, 0x31 is the NULL address; however, the CX28229 can be configured to treat valid port address. The following three configurations are available: UTOPIA-to-Serial UTOPIA-to-UTOPIA Stand-alone Cell Delineation only 2.1 ...
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... CX2822x Hardware Description Figure 2-1. CX28229 Logic Diagram (UTOPIA-to-UTOPIA) Reset I 8kHzIn Clock I PHY Transmit Clock O PHY Transmit Enable O PHY Transmit Address Bus O O PHY Receive Clock PHY Receive Enable O PHY Receive Address Bus O Phy Interface Select I I Sync/Async Mode Select I Microprocessor Clock ...
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... Mindspeed reference designs available online. Configuration information is shown in 28229-DSH-001-D is the pinout diagram for the CX28229 when operating in the UTOPIA-to- UTOPIA-to-UTOPIA configuration is selected by tying the PhyIntFcSel pin low block diagram port IMA solution using the device in the Table 2-2 ...
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... Figure 2-2. IMA Block Diagram Table 2-2. UTOPIA-to-UTOPIA Configuration Information ATMMux [7,6] PhyIntFcSel (ATMINTFC, 0x202) (Pin R4) 01 Low Use of external memory is optional. GENERAL NOTE: 2-4 Description IMA UTOPIA using the PHY Side UTOPIA; Internal TC block and serial ports not used. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
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... CX28224/5/9 Data Sheet Figure 2-3. CX28229 Pinout Diagram UTOPIA-to-UTOPIA (Top View MW/R, MRd* atmURxAddr[1] A MAS*, MWr* TxTRL[1] atmURxAddr[2] MCS* B MicroAddr[0] VGG MicroAddr[1] atmURxPrty C MicroAddr[4] atmURxAddr[3] atmURxAddr[0] MicroAddr[3] D MicroAddr[5] atmURxAddr[4] MicroAddr[8] MicroAddr[2] E MicroAddr[6] MicroAddr[9] MemAddr[1] MicroAddr[7] F MemAddr[4] MemAddr[0] MemAddr[5] MemAddr[2] G MemAddr[3} ...
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... When asserted high, the device will not respond to input signal transitions on MicroClk, MW/R, MRd*, or MAS*, MWr*. Additionally, when MCS* is asserted high, the MicroData[7:0] pins are in a high- impedance state but the MicroInt* pin remains operational. Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... When active low, the device needs servicing. It remains active until the pending interrupt is processed by the Interrupt Service Routine. This pin is an open drain output for an external wired OR logic implementation. An external pull-up resistor is required for this pin. Mindspeed Technologies ™ CX2822x Hardware Description Description - ...
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... Differential delay SRAM Data Bus. ATM cells extracted from the Receive data stream are stored in the SRAM for P6 the purpose of differential delay compensation N10 T10 R10 P11 N11 T11 R11 P12 N12 A6 B6 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... This signal is enabled by pulling the ExtMemSel pin high Receive SRAM clock signal. This signal is enabled by pulling the ExtMemSel pin high Receive SRAM address enable (active low) address strobe. This signal is enabled by pulling the ExtMemSel pin high. Mindspeed Technologies ™ CX2822x Hardware Description Description - 2 9 ...
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... Receive PHY Cell Bus address. The following limitations apply: T7 Device P8 T8 CX28224 R8 CX28225 CX28229 N9 I Cell Available signals for Receive PHY interfaces. phyURxClAv{n] is active when one or more complete cells T16 I/PD can be transferred. To support different PHY devices, separate cell available signals are provided. This allows expansion to 32 points ...
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... T13 Device R13 L15 CX28224 K13 CX28225 CX28229 R14 I Cell Available signals for Transmit ATM cells. When phyUTxClAv[n] is active high, the PHY has space available R15 I/PD for one or more complete cells. To support different PHY devices, separate cell available signals are provided. ...
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... K14 I/PD When using the PHY UTOPIA mode, this pin is a no- connect. L16 K15 J13 K16 J14 J16 I/PD When using the PHY UTOPIA mode, this pin is a no- connect. J15 H13 H14 H16 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description Chapter 3. 3. 28229-DSH-001-D ...
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... A13 I Parity status signal bit Utopia mode, a parity calculation is performed over atmUTxData[7:0] for each clock cycle of atmUTxClk. Odd parity is used bit Utopia mode, this signal is the parity of atmUTxData[15:0]. This signal is optional. Mindspeed Technologies ™ CX2822x Hardware Description Description - 2 13 ...
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... ATM Utopia addresses 8–15 only. In this mode, atmURxClAv[1] will threestate for addresses 0– Data transfer and output enable for receive ATM cells (active low). Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... This signal is optional Receive ATM Cell Bus address. This address determines the source channel of the Receive ATM cells output from A4 the IMA subsystem and also selects the channel sourcing the atmURxClAv signal Mindspeed Technologies ™ CX2822x Hardware Description Description - 2 15 ...
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... G12 H5 H6 H11 H12 J5 J6 J11 J12 K5 K6 K11 K12 E5 Power supply connections. (3 E10 E11 E12 F10 F11 F12 L10 L11 L12 M10 M11 M12 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
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... G10 H10 J10 K10 B3 Provides ESD protection when interfacing with 5 V systems. If using this device in a system with 5 V logic, this pin must be connected using 3.3 V system, connect to 3.3 V. Mindspeed Technologies ™ CX2822x Hardware Description Description - 2 17 ...
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... These framers could be T1/E1 or DSL. Further details can be found in the Mindspeed reference design available online. Configuration information is shown in Table 2-4. 2-18 illustrates a pinout diagram for the CX28229 when operating in UTOPIA- UTOPIA-to-Serial configuration is selected by tying the PhyIntFcSel pin high block diagram link IMA solution using the device in the Mindspeed Technologies ™ ...
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... CX28224/5/9 Data Sheet Figure 2-4. CX28229 Logic Diagram (UTOPIA-to-Serial) Reset I 8kHzIn Clock I Receive Clock I Receive Data I Receive Data Marker I Receive Clock I Receive Data I Receive Data Marker I PHY Interface Select I I Sync/Async Mode Select I Microprocessor Clock I Chip Select I Address Strobe, Write Control ...
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... Engine Tx Block IMA clocks Table 2-4. CX28229 UTOPIA-to-Serial Mode ATMMux [7,6] PhyIntFcSel (ATMINTFC, 0x202) (Pin R4) 01 High External memory could be used if desired (CX28229). GENERAL NOTE: 2-20 Extended Memory IMA Block 1 TC Counters Micro interface JTAG IMA UTOPIA using Internal TC block; UTOPIA-to-Serial mode using 8 internal serial ports ...
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... CX28224/5/9 Data Sheet Figure 2-6. CX28229 Pinout Diagram, UTOPIA-to-Serial (Top View MW/R, MRd* atmURxAddr[1] A MAS*, MWr* TxTRL[1] atmURxData[6] atmURxAddr[2] MCS* B MicroAddr[0] VGG atmURxData[7] MicroAddr[1] atmURxPrty C MicroAddr[4] atmURxData[4] atmURxAddr[3] MicroAddr[3] atmURxAddr[0] D MicroAddr[5] atmURxAddr[4] atmURxData[5] MicroAddr[8] MicroAddr[2] E MicroAddr[9] MicroAddr[6] MemAddr[1] MicroAddr[7] F MemAddr[4] ...
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... CX2822x Hardware Description Table 2-5. CX28229 Pin Descriptions (1 of 12) Pin Label Signal Name StatOut[0] Status Output StatOut[1] MSyncMode Microprocessor Synchronous/ Asynchronous Bus Mode Select Reset* Device Reset 8kHzIn 8 kHz Input OneSecIO One-Second Input/ Output MW/R, MRd* Microprocessor Write/Read MCS* Microprocessor Chip Select 2-22 No. ...
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... CX28224/5/9 Data Sheet Table 2-5. CX28229 Pin Descriptions (2 of 12) Pin Label Signal Name MAS*, MWr* Microprocessor Address Strobe MicroAddr[0] Microprocessor Address Bus MicroAddr[1] MicroAddr[2] MicroAddr[3] MicroAddr[4] MicroAddr[5] MicroAddr[6] MicroAddr[7] MicroAddr[8] MicroAddr[9] MicroAddr[10] MicroData[0] Microprocessor Data Bus MicroData[1] MicroData[2] MicroData[3] MicroData[4] MicroData[5] MicroData[6] ...
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... CX2822x Hardware Description Table 2-5. CX28229 Pin Descriptions (3 of 12) Pin Label Signal Name MRdy Microprocessor Ready MicroClk Microprocessor Clock ExtMemSel External Memory Enable MemData[0] Differential Delay Memory Data Bus MemData[1] MemData[2] MemData[3] MemData[4] MemData[5] MemData[6] MemData[7] MemData[8] MemData[9] MemData[10] MemData[11] MemData[12] MemData[13] ...
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... CX28224/5/9 Data Sheet Table 2-5. CX28229 Pin Descriptions (4 of 12) Pin Label Signal Name MemAddr[0] Differential Delay Memory Address Bus MemAddr[1] MemAddr[2] MemAddr[3] MemAddr[4] MemAddr[5] MemAddr[6] MemAddr[7] MemAddr[8] MemAddr[9] MemAddr[10] MemAddr[11] MemAddr[12] MemAddr[13] MemAddr[14] MemAddr[15] MemAddr[16] MemAddr[17] MemAddr[18] MemAddr[19] MemCtrl_CE* Chip Enable MemCtrl_OE* ...
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... CX2822x Hardware Description Table 2-5. CX28229 Pin Descriptions (5 of 12) Pin Label Signal Name TRST* Test Reset TCK Test Clock TMS Test Mode Select TDI Test Data Input TDO Test Data Output TestEnable TestMode PhyIntFcSel PHY Interface Select phyURxEnb[1]* PHY UTOPIA Receive Enable ...
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... CX28224/5/9 Data Sheet Table 2-5. CX28229 Pin Descriptions (6 of 12) Pin Label Signal Name SPRxSync[0] Frame Sync Input SPRxSync[1] SPRxSync[2] SPRxSync[3] SPRxSync[4] SPRxSync[5] SPRxSync[6] SPRxSync[7] SPRxClk[0] Receive Line Clock Input SPRxClk[1] SPRxClk[2] SPRxClk[3] SPRxClk[4] SPRxClk[5] SPRxClk[6] SPRxClk[7] 28229-DSH-001-D No. I/O T12 I/PD When the PHY serial interface is enabled, this is the frame sync input ...
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... CX2822x Hardware Description Table 2-5. CX28229 Pin Descriptions (7 of 12) Pin Label Signal Name SPRxData[0] Receive Line Data Input SPRxData[1] SPRxData[2] SPRxData[3] SPRxData[4] SPRxData[5] SPRxData[6] SPRxData[7] SPTxSync[0] Frame Sync Input/ Output SPTxSync[1] SPTxSync[2] SPTxSync[3] SPTxSync[4] SPTxSync[5] SPTxSync[6] SPTxSync[7] SPTxData[0] Transmit Line Data Output ...
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... CX28224/5/9 Data Sheet Table 2-5. CX28229 Pin Descriptions (8 of 12) Pin Label Signal Name atmUTxAddr[0] ATM UTOPIA Transmit Address atmUTxAddr[1] atmUTxAddr[2] atmUTxAddr[3] atmUTxAddr[4] atmUTxData[0] ATM UTOPIA Transmit Data atmUTxData[1] atmUTxData[2] atmUTxData[3] atmUTxData[4] atmUTxData[5] atmUTxData[6] atmUTxData[7] atmUTxData[8] atmUTxData[9] atmUTxData[10] atmUTxData[11] atmUTxData[12] atmUTxData[13] atmUTxData[14] atmUTxData[15] ...
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... CX2822x Hardware Description Table 2-5. CX28229 Pin Descriptions (9 of 12) Pin Label Signal Name atmUTxClAv ATM UTOPIA Transmit Cell Available atmUTxSOC ATM UTOPIA Transmit Start of Cell atmUTxEnb* ATM UTOPIA Transmit Enable atmUTxClk ATM UTOPIA Transmit Clock atmURxSOC ATM UTOPIA Receive Start of Cell atmURxClk ...
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... CX28224/5/9 Data Sheet Table 2-5. CX28229 Pin Descriptions (10 of 12) Pin Label Signal Name atmURxData[0] ATM UTOPIA Receive Data atmURxData[1] atmURxData[2] atmURxData[3] atmURxData[4] atmURxData[5] atmURxData[6] atmURxData[7] atmURxData[8] atmURxData[9] atmURxData[10] atmURxData[11] atmURxData[12] atmURxData[13] atmURxData[14] atmURxData[15] atmURxPrty ATM UTOPIA Receive Parity atmURxAddr[0] ATM UTOPIA Receive ...
Page 60
... CX2822x Hardware Description Table 2-5. CX28229 Pin Descriptions (11 of 12) Pin Label Signal Name V (1.8 V) Supply Voltage (1 (3.3 V) Supply Voltage (3 2-32 No. I/O G5 Power supply connections. (1 G11 G12 H5 H6 H11 H12 J5 J6 J11 J12 K5 K6 K11 K12 E5 Power supply connections. (3 ...
Page 61
... CX28224/5/9 Data Sheet Table 2-5. CX28229 Pin Descriptions (12 of 12) Pin Label Signal Name V GND Ground ss VGG Electrostatic Discharge (ESD) Supply Voltage FOOTNOTE: (1) This bus is enabled by pulling the ExtMemSel pin high. External Memory is disabled on the CX28224 and CX28225 versions of the device. 28229-DSH-001-D No. ...
Page 62
... R4) 10 High 2- example of a non-IMA application. The CX28229 is being used as a Most applications would use the less expensive RS8228 or M28228 Cell delineator. However, there may be applications that require the flexibility of the CX28229. This mode is also useful for troubleshoot during development since the IMA software drivers are not required. ...
Page 63
... Purpose mode and MicroClk used as the clock to loop back cells result of the automatic mode switch and clock used, the data on the Tx serial lines will be corrupted. ATM Cell Transmitter ATM Cell Receiver Cell Cell Validation Alignment VPI/VCI Screening Mindspeed Technologies ™ CX2822x Hardware Description UTOPIA Level 2 Interface Host Interface atmUTxClk ...
Page 64
... SPTxClk, SPRxClk, SPTxSync, and SPRxSync must be present for the loopback mode to function properly for a given port. ATM Cell Transmitter ATM Cell Receiver Cell Cell Validation Alignment VPI/VCI Screening Mindspeed Technologies ™ CX28224/5/9 Data Sheet UTOPIA Level 2 Interface IMA Interface atmUTxClk Transmit ...
Page 65
... CX28224/5/9 Data Sheet 2.7 Application Overview The CX2822x is typically used with line framer devices like the CX28398 T1/E1 octal transceiver, the Bt8970 Zip Wire or the CX28398 HDLC Framer. illustrates a typical application. Figure 2-10. CX2822x Connected to a CX28398 Transceiver CX28229 UTOPIA Level 2 Bus ATM Switch or SAR Processor Microprocessor Bus 2 ...
Page 66
... CX2822x Hardware Description 2-38 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 67
... IMA frame rate of the received IMA group. Using this option for the Transmit IMA group frame rate results in a 'line timed' configuration. 28229-DSH-001-D Figure 8 kHz) reference clock from which nominal Transmit x Mindspeed Technologies ™ 3-1. While this can appear ...
Page 68
... This block generates a bit rate clock that is phase locked to the PHY side RxClAv signal. It can monitor Loop all 32 ports on the bus. Any port can be selected as the group timing reference. 3-2 shows the details of the CX28229's IMA clock block from Table Description Mindspeed Technologies ™ ...
Page 69
... CX28224/5/9 Data Sheet Figure 3-1. CX28229 Clock Diagram IMA Engine RX Mux Note 1 28229-DSH-001-D TX Mux Note 1 Mindspeed Technologies ™ IMA Clocks 500027_072 - 3 3 ...
Page 70
... This is one of the simplest implementation of IMA when a clock equal to 24 times the line rate is available. Several issues are worth noting: The IMA_RefClk input is unused and should be tied to ground. The CX28229 is deriving all required clocks from the Serial port clocks and the IMA_SysClk. ...
Page 71
... Figure 3-2. T1/E1 using Internal Serial ports; IMA_SysClk equals 24x line rate SPRxClk 0 IMA_RefClk NOT USED; tie to ground IMA_SysClk 24 x line rate General Note: 1. SPRxClk 1-7 are identical but not shown for clarity. 28229-DSH-001-D Transition Synchronizer Detector ref /16 /24 Mindspeed Technologies ™ IMA Clocks Note 1 Note 1 500027_073 - 3 5 ...
Page 72
... The device is configured using a software driver. The following code is an example of calls to the driver: IMA_LINK_TYPE = IMA_DS1 IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE IMA_DSL_REF_GENERATOR = IMA_INACTIVE IMA_ALT_RX_TRL = IMA_INACTIVE IMA_GRP_TX_TRL_SRC = IMA_REF_CLK1 (grp#) IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#) 3-6 illustrates T1/E1 with internal serial ports, using IMA_RefClk. There are Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 73
... Figure 3-3. T1/E1 using Internal Serial ports; IMA_RefClk equals line rate Transition SPRxClk 0 Detector IMA_RefClk IMA_SysClk > line rate Transition Detector General Note: 1. SPRxClk 1-7 are identical but not shown for clarity. 28229-DSH-001-D Synchronizer ref ref Synchronizer Mindspeed Technologies ™ IMA Clocks Note 1 Note 1 500027_074 - 3 7 ...
Page 74
... IMA_LINK_TYPE = IMA_VAR_RATE IMA_DSL_REF_CLK_FREQUENCY = 40960000 IMA_DSL_USE_REF_CLK2 = IMA_INACTIVE IMA_DSL_REF_GENERATOR = IMA_ACTIVE IMA_ALT_RX_TRL = IMA_ACTIVE IMA_GRP_LINK_BANDWIDTH = 2304 (grp#) IMA_GRP_CLK_REF_FACTOR = IMA_NO_DIV (grp#) IMA_GRP_TX_TRL_SRC = IMA_REF_XCLK (grp#) IMA_GRP_RX_TRL_SRC = IMA_RX_TRL_(x) (grp#) 3-8 illustrates the configuration most commonly used with applications that Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 75
... SPRxClk 1-7 are identical but not shown for clarity. 2. NCO - Numerically controlled oscillator; controlled by parameters in Register 416 and 417. 28229-DSH-001-D up/down adjust n*8kHz NCO See Note 2. Synchronizer ref n*8kHz NCO See Note 2. Mindspeed Technologies ™ IMA Clocks Phase Comparitor /424 Note 1 Note 1 500027_075 - 3 9 ...
Page 76
... IMA Clocks 3-10 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 77
... PHY side UTOPIA—This interface is selected when the TC block is disabled and the designer wishes to interface to a device via an UTOPIA interface. This allows the CX28229 IMA engine to address ports on the line side. 28229-DSH-001-D By convention, data being transferred from the PHY to the ATM layer is considered received data, while data from the ATM layer to the PHY is called transmitted data ...
Page 78
... In 16-bit mode, the cell consists of 54 bytes. The first five bytes contain header information. The sixth byte, UDF2, is required to maintain alignment but is not read by the CX2822x. The remaining bytes are used for payload. 4-2 Figure 4-1. CX28224 only supports 8 bit UTOPIA. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 79
... If only one channel is programmed, (a single IMA group and no pass-through facilities), then the CX28229 can be compatible with UTOPIA Level 1 by fixing the address lines to a specific value and setting the IMA group’s ATM address (through the software driver) to that value. ...
Page 80
... IMA UTOPIA using the PHY Side UTOPIA; UTOPIA-to-UTOPIA; TC block/serial ports not used. IMA UTOPIA using Internal TC block; UTOPIA-to-Serial mode; 8 internal serial ports TC only; Device used as Stand-alone cell delineator with 8 serial ports; IMA block not used. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 81
... UTOPIA uses address 0x31 as the null address thus limiting the bus to 31 ports. However, the standard also allows for multiple ClAv and Enable lines.) Figure 4-1. CX28229 Multiple UTOPIA Control Lines ATM Layer UTOPIA bus General Note: Only the Transmit side is shown for clarity ...
Page 82
... UTOPIA Interfaces 4-6 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 83
... ATM layer. Whether the original header cells or replacement cells are sent is controlled by bits 0–4 in the HDRFIELD (0x09) register. 28229-DSH-001-D When operating in the UTOPIA-to-UTOPIA mode, the ATM Cell processor block is disabled. Mindspeed Technologies ™ ...
Page 84
... Microprocessor Interface Status and Control ATM Cell Transmitter ATM Cell Receiver Cell Cell Validation Alignment VPI/VCI Screening One Second Interface 8kHzIn TDO TDI Mindspeed Technologies ™ CX28224/5/9 Data Sheet Control Lines UTOPIA Level 2 Interface IMA Transmit atmUTxClk UTOPIA atmUTxClAv 4-cell Level 2 ...
Page 85
... Distributed Sample Scrambler [DSS]) unscrambled. This means that the only repetitive byte patterns in the data stream that meet the cell delineation criteria are valid headers (or just the HEC bytes in DSS). 28229-DSH-001-D 1 Correct HEC Pre-Sync 1 Errored HEC 7 Errored HECs Mindspeed Technologies ™ Transmission Convergence Block Figure 5-2). 6 Correct HECs Sync 500027_006 Figure 5-3 ...
Page 86
... Once byte-alignment is achieved, cell delineation is performed. 5.2.2 Processing Non-Standard Traffic Using the CX28229 The CX28229 contains two independent "HEC Check" state machines. The Cell Delineator (CD) State Machine is used to find Cell Delineation and, conversely, to declare loss of cell delineation (LOCD). The other is the Cell Valid (CV) State Machine, which is used to validate the cells to pass to the UTOPIA FIFOs ...
Page 87
... All data received will be passed across the UTOPIA bus in blocks of 53 bytes. No attempt is made to find ATM cells. GENERAL NOTE: 1. The HEC Error Correction circuit is independent of the DisHECChk control bit. The CX28229 will correct single bit errors even when the DisHECChk is enabled (assuming that the EnHECCor bit is set to 1). 28229-DSH-001-D ...
Page 88
... Table 5-3. Receive Cell Header Bit Cell Reject Header Match 0 Match 1 Fail 0 Fail 1 Mindspeed Technologies CX28224/5/9 Data Sheet Incoming Bit Result 0 Match 1 Fail 0 Fail 1 Match x Match Result Accept Cell Reject Cell Reject Cell Accept Cell ™ 28229-DSH-001-D ...
Page 89
... If DSS descrambling fails, the CX2822x defaults to unscrambled mode. 28229-DSH-001-D If both SSS and DSS are enabled, SSS overrides DSS scramble the payload, leaving the five + × polynomial to scramble the entire cell, except Mindspeed Technologies ™ Transmission Convergence Block - 5 7 ...
Page 90
... Mbps. Each of the eight ports can be configured for a different mode. 5.2.5.1 T1/E1 Interface This describes the timing requirements of the CX28229 when operating mode. Connection to a CN8370 T1/E1 framer is used as an example, as illustrated in Figure 5-4. The CX28229 receives a T1/E1 data stream from the external framer, ignores the T1/E1 overhead, extracts the ATM cells, and passes the ATM cells to the ATM layer device. In the transmit direction, the CX28229 inserts 0’ ...
Page 91
... Tx Frame Marker SPTxSync Serial Data SPTxData Rx Frame Marker SPRxSync Serial Data SPRxData Clock SPTxClk, SPRxClk Clock Source TS0/1 MSB/F 255 192 TS0/1 MSB/F 255 192 Mindspeed Technologies ™ Transmission Convergence Block CX28229 PORT X LSB 248 185 LSB 248 185 500027_065 - 5 9 ...
Page 92
... SPRxSync T 2 SPRxData Overhead General Notes: The diagram shows the CX28229 programmed to sample on the rising edge of the clock. The Overhead bit is sampled on the clock edge 0. For T , SPRxSync must occur at least 10 ns after the rising edge of the 193rd clock must have a minimum of 1 clock period. ...
Page 93
... DSL Modem (1) Bit Clock SPTxSync MSB Tx Serial Data Rx Serial Data (2) SPRxSync General Notes: (1) The CX28229 operates at data rates Mbps. (2) Polarity is shown as active low in above figure. 3. TxSync indicates the Start of Cell and Rx are asynchronous. 28229-DSH-001-D Tx Serial Data TxData SPTxData TxSync SPTxSync ...
Page 94
... Rx Serial Data General Notes: (1) The 1168 kbps limit is imposed by the Bt8970; the CX28229 operates at data rates Mbps general purpose mode, SPTxSync and SPRxSync should be tied high and Register IOMODE bits (6 and 4) should be set to 0 (default). 3. Diagram shows default values for TxClkPol and RxClkPol (IOMODE register). ...
Page 95
... The PrtLgcRst, bit 6, in the PMODE register (0x04) restarts all functions but leaves the port control registers unaffected. 28229-DSH-001-D The MicroClk is required for both modes. In asynchronous mode, a MicroClk frequency 50MHz, must be present but can be asynchronous to the other microprocessor signals. In synchronous mode, MicroClk is limited to 25MHz. Mindspeed Technologies ™ ...
Page 96
... See Bit 0 of the Mode register (0x200). NOTE: 6-2 When latching is disabled and a counter is wider than one byte, the LSB should be read first to retain the values of the other bytes for a subsequent read. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 97
... EnIntPin (bit 3) in the MODE register (0x202). Figure 6-1 illustrates the registers involved in the interrupt generation process. 28229-DSH-001-D The IMA block does not generate interrupts. illustrates the flow chart of the interrupt generation process and Mindspeed Technologies ™ General Issues Figure 6 ...
Page 98
... Set Individual Interrupt Indication Bit SUMINT No Interrupt Indication Enabled ? Yes Set SUMINT Interrupt Indication Bit SUMPORT No Port Indication Enabled ? Yes Set SUMPORT Interrupt Indication Bit Interrupt No Pin (MInt*) Enabled ? Yes Set Interrupt Pin (MInt*) Mindspeed Technologies ™ CX28224/5/9 Data Sheet Return 500027_015 28229-DSH-001-D ...
Page 99
... PortInt[0] by ENSUMPORT (0x0201) SUMINT (0x0000) Reserved 7 Reserved 6 EnIntPin Reserved 5 Reserved 4 OR OneSecInt 3 (1) ExInt 2 TxCellInt 1 RxCellInt 0 Input to latch Enabled by ENSUMINT (0x0001) Mindspeed Technologies ™ General Issues MInt Input to latch Enabled MODE (0x0202 500027_016 ...
Page 100
... OneSecInt and ExInt are cleared when the register is read. However, the TxCellInt and RxCellInt bits are cleared only when the corresponding Level 1 register is read and cleared. Level 3 bits are cleared when the entire corresponding Level 2 register has been read and cleared. 6-6 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 101
... IMA Control and Status Registers 28229-DSH-001-D Table 7-3 lists the port-level control and status registers. Control bits that do not have a documented function are reserved and must be written to a logical 0. Description Mindspeed Technologies ™ Table 7-1 lists Table 7-2 lists the device-level Port Base Address ...
Page 102
... Header Field Control Register — Transmit Idle Cell Payload Control Register — Error Pattern Control Register — Cell Validation Control Register — UTOPIA Control Register 1 — UTOPIA Control Register 2 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-64 page 7-65 page 7-65 page 7-65 page 7-66 page 7-66 ...
Page 103
... Transmit Cell Interrupt Indication Control Register — Receive Cell Interrupt Indication Control Register (1) Transmit Cell Status Control Register (1) Receive Cell Status Control Register (2) Idle Cell Receive Counter (low byte) Mindspeed Technologies ™ Registers Page Number page 7-41 page 7-41 page 7-42 page 7-42 page 7-43 ...
Page 104
... Non-Matching Cell Counter (high byte) — Reserved, set to a logical 0 — Reserved, set to a logical 0 lists several registers used for CX2822x’s basic functions, including Description lists the control registers used for transmission of traffic. Mindspeed Technologies CX28224/5/9 Data Sheet Page Number page 7-57 page 7-58 page 7-58 page 7-59 ...
Page 105
... Receive Idle Cell Mask Control Register 2 0x26 IDLMSK3 Receive Idle Cell Mask Control Register 3 0x27 IDLMSK4 Receive Idle Cell Mask Control Register 4 28229-DSH-001-D Description lists the control registers used for reception of traffic. Description Mindspeed Technologies Registers Page Number page 7-37 page 7-38 page 7-38 page 7-39 page 7-41 page 7-42 page 7-42 ...
Page 106
... UTOPIA operations. Description lists interrupt enables, interrupt indications, and status information. Description lists the CX2822x’s counters. When the counters fill, they saturate and do Description Mindspeed Technologies CX28224/5/9 Data Sheet Page Number page 7-40 page 7-40 Page ...
Page 107
... ATM Utopia Control Diff. Delay Control Address Diff. Delay Control Data DSL Clock Generator Control Address DSL Clock Generator Control Data Receive Translation Table Address Receive Translation Table Internal Channel Transmit Translation Table Address Mindspeed Technologies ™ Registers Page Number page 7-61 page 7-62 page 7-63 ...
Page 108
... IMA_GRP_13TO16_SEM 7-8 Description (Continued) Transmit Translation Table Internal Channel Link Table Control Groups 1–4 Table Control Groups 5–8 Table Control Groups 9–12 Table Control Groups 13–16 Table Control Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-86 page 7-109 page 7-88 page 7-89 page 7-90 ...
Page 109
... Tx GRP 3 Tx Test Pattern Tx GRP 4 Rx Test Pattern Tx GRP 4 Control Tx GRP 4 First Link Address Tx GRP 4 Tx Group ID Tx GRP 4 Status / Control Tx GRP 4 Timing Control Tx GRP 4 Test Control Tx GRP 4 Tx Test Pattern Mindspeed Technologies ™ Registers Page Number page 7-92 page 7-93 page 7-94 page 7-95 ...
Page 110
... Group 2 Receive Cell Count LSBs Group 2 Receive Cell Count MSBs Group 3 Receive Cell Count LSBs Group 3 Receive Cell Count MSBs Group 4 Receive Cell Count LSBs Group 4 Receive Cell Count MSBs Loss of PhyURxSOC Detector Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-99 page 7-100 ...
Page 111
... Rx Link 4 Status Rx Link 5 Status Rx Link 6 Status Rx Link 7 Status Rx Link 0 Defects Rx Link 1 Defects Rx Link 2 Defects Rx Link 3 Defects Rx Link 4 Defects Rx Link 5 Defects Rx Link 6 Defects Rx Link 7 Defects Mindspeed Technologies ™ Registers Page Number page 7-110 page 7-111 page 7-112 page 7-113 page 7-114 page 7-115 - ...
Page 112
... Rx Link 1 Captured GRP ID Rx Link 2 Captured GRP ID Rx Link 3 Captured GRP ID Rx Link 4 Captured GRP ID Rx Link 5 Captured GRP ID Rx Link 6 Captured GRP ID Rx Link 7 Captured GRP ID Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-116 page 7-117 page 7-118 ...
Page 113
... Rx GRP 2 Rx Group ID Rx GRP 3 Configuration Rx GRP 3 Control Rx GRP 3 First Link Address Rx GRP 3 Rx Group ID Rx GRP 4 Configuration Rx GRP 4 Control Rx GRP 4 First Link Address Rx GRP 4 Rx Group ID Mindspeed Technologies ™ Registers Page Number page 7-101 page 7-102 page 7-103 page 7-104 ...
Page 114
... Rx GRP 3 Tx Test Pattern Rx GRP 4 Rx Test Pattern Rx GRP 4 SCCI Rx GRP 4 Rx Group ID Rx GRP 4 Status / Control Rx GRP 4 Timing Control Rx GRP 4 Test Control Rx GRP 4 Tx Test Pattern Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-104 page 7-105 page 7-105 ...
Page 115
... Tx GRP 7 Tx Test Pattern Tx GRP 8 Rx Test Pattern Tx GRP 8 Control Tx GRP 8 First Link Address Tx GRP 8 Tx Group ID Tx GRP 8 Status / Control Tx GRP 8 Timing Control Tx GRP 8 Test Control Tx GRP 8 Tx Test Pattern Mindspeed Technologies ™ Registers Page Number page 7-92 page 7-93 page 7-94 page 7-95 ...
Page 116
... Group 6 Receive Cell Count LSBs Group 6 Receive Cell Count MSBs Group 7 Receive Cell Count LSBs Group 7 Receive Cell Count MSBs Group 8 Receive Cell Count LSBs Group 8 Receive Cell Count MSBs Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-99 page 7-100 ...
Page 117
... Rx Link 12 Status Rx Link 13 Status Rx Link 14 Status Rx Link 15 Status Rx Link 8 Defects Rx Link 9 Defects Rx Link 10 Defects Rx Link 11 Defects Rx Link 12 Defects Rx Link 13 Defects Rx Link 14 Defects Rx Link 15 Defects Mindspeed Technologies ™ Registers Page Number page 7-110 page 7-111 page 7-112 page 7-113 page 7-114 page 7-115 - ...
Page 118
... Rx Link 9 Captured GRP ID Rx Link 10 Captured GRP ID Rx Link 11 Captured GRP ID Rx Link 12 Captured GRP ID Rx Link 13 Captured GRP ID Rx Link 14 Captured GRP ID Rx Link 15 Captured GRP ID Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-116 page 7-117 page 7-118 ...
Page 119
... Rx GRP 6 Rx Group ID Rx GRP 7 Configuration Rx GRP 7 Control Rx GRP 7 First Link Address Rx GRP 7 Rx Group ID Rx GRP 8 Configuration Rx GRP 8 Control Rx GRP 8 First Link Address Rx GRP 8 Rx Group ID Mindspeed Technologies ™ Registers Page Number page 7-101 page 7-102 page 7-103 page 7-104 ...
Page 120
... Rx GRP 7 Tx Test Pattern Rx GRP 8 Rx Test Pattern Rx GRP 8 SCCI Rx GRP 8 Rx Group ID Rx GRP 8 Status / Control Rx GRP 8 Timing Control Rx GRP 8 Test Control Rx GRP 8 Tx Test Pattern Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-104 page 7-105 page 7-105 ...
Page 121
... Tx GRP 11 Tx Test Pattern Tx GRP 12 Rx Test Pattern Tx GRP 12 Control Tx GRP 12 First Link Address Tx GRP 12 Tx Group ID Tx GRP 12 Status / Control Tx GRP 12 Timing Control Tx GRP 12 Test Control Tx GRP 12 Tx Test Pattern Mindspeed Technologies Registers Page Number page 7-92 page 7-93 page 7-94 page 7-95 page 7-96 ...
Page 122
... Group 10 Receive Cell Count LSBs Group 10 Receive Cell Count MSBs Group 11 Receive Cell Count LSBs Group 11 Receive Cell Count MSBs Group 12 Receive Cell Count LSBs Group 12 Receive Cell Count MSBs Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-99 page 7-100 ...
Page 123
... Rx Link 20 Status Rx Link 21 Status Rx Link 22 Status Rx Link 23 Status Rx Link 16 Defects Rx Link 17 Defects Rx Link 18 Defects Rx Link 19 Defects Rx Link 20 Defects Rx Link 21 Defects Rx Link 22 Defects Rx Link 23 Defects Mindspeed Technologies ™ Registers Page Number page 7-110 page 7-111 page 7-112 page 7-113 page 7-114 page 7-115 - ...
Page 124
... Rx Link 17 Captured GRP ID Rx Link 18 Captured GRP ID Rx Link 19 Captured GRP ID Rx Link 20 Captured GRP ID Rx Link 21 Captured GRP ID Rx Link 22 Captured GRP ID Rx Link 23 Captured GRP ID Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-116 page 7-117 page 7-118 ...
Page 125
... Rx GRP 10 Rx Group ID Rx GRP 11 Configuration Rx GRP 11 Control Rx GRP 11 First Link Address Rx GRP 11 Rx Group ID Rx GRP 12 Configuration Rx GRP 12 Control Rx GRP 12 First Link Address Rx GRP 12 Rx Group ID Mindspeed Technologies Registers Page Number page 7-101 page 7-102 page 7-103 page 7-104 page 7-101 ...
Page 126
... Rx GRP 11 Tx Test Pattern Rx GRP 12 Rx Test Pattern Rx GRP 12 SCCI Rx GRP 12 Rx Group ID Rx GRP 12 Status / Control Rx GRP 12 Timing Control Rx GRP 12 Test Control Rx GRP 12 Tx Test Pattern Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-104 page 7-105 page 7-105 ...
Page 127
... Tx GRP 15 Tx Test Pattern Tx GRP 16 Rx Test Pattern Tx GRP 16 Control Tx GRP 16 First Link Address Tx GRP 16 Tx Group ID Tx GRP 16 Status / Control Tx GRP 16 Timing Control Tx GRP 16 Test Control Tx GRP 16 Tx Test Pattern Mindspeed Technologies Registers Page Number page 7-92 page 7-93 page 7-94 page 7-95 page 7-96 ...
Page 128
... Group 14 Receive Cell Count LSBs Group 14 Receive Cell Count MSBs Group 15 Receive Cell Count LSBs Group 15 Receive Cell Count MSBs Group 16 Receive Cell Count LSBs Group 16 Receive Cell Count MSBs Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-99 page 7-100 ...
Page 129
... Rx Link 28 Status Rx Link 29 Status Rx Link 30 Status Rx Link 31 Status Rx Link 24 Defects Rx Link 25 Defects Rx Link 26 Defects Rx Link 27 Defects Rx Link 28 Defects Rx Link 29 Defects Rx Link 30 Defects Rx Link 31 Defects Mindspeed Technologies ™ Registers Page Number page 7-110 page 7-111 page 7-112 page 7-113 page 7-114 page 7-115 - ...
Page 130
... Rx Link 25 Captured GRP ID Rx Link 26 Captured GRP ID Rx Link 27 Captured GRP ID Rx Link 28 Captured GRP ID Rx Link 29 Captured GRP ID Rx Link 30 Captured GRP ID Rx Link 31 Captured GRP ID Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-116 page 7-117 page 7-118 ...
Page 131
... Rx GRP 14 Rx Group ID Rx GRP 15 Configuration Rx GRP 15 Control Rx GRP 15 First Link Address Rx GRP 15 Rx Group ID Rx GRP 16 Configuration Rx GRP 16 Control Rx GRP 16 First Link Address Rx GRP 16 Rx Group ID Mindspeed Technologies Registers Page Number page 7-101 page 7-102 page 7-103 page 7-104 page 7-101 ...
Page 132
... Rx GRP 15 Tx Test Pattern Rx GRP 16 Rx Test Pattern Rx GRP 16 SCCI Rx GRP 16 Rx Group ID Rx GRP 16 Status / Control Rx GRP 16 Timing Control Rx GRP 16 Test Control Rx GRP 16 Tx Test Pattern Mindspeed Technologies ™ CX28224/5/9 Data Sheet Page Number page 7-104 page 7-105 page 7-105 ...
Page 133
... TxCellInt register (0x2C). When a logical 1 is read, this bit indicates a Receive Cell Interrupt. This interrupt is a summary interrupt and signifies that an interrupt indication occurred in the RxCellInt register (0x2D). Mindspeed Technologies ™ Registers - 7 ...
Page 134
... When written to a logical 1, this bit enables the receive cell interrupts located in the RxCellInt register (0x2D). These interrupts can appear on the MicroInt* pin (pin T1), provided that EnPortInt in the ENSUMPORT register (0x0201) is enabled for this port and EnIntPin (bit 3) in the MODE register (0x0202) is enabled. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 135
... Purpose In General Purpose Mode, the SPRxSync and SPTxSync pins are ignored. (However, good design practice would have them tied high.) Mindspeed Technologies ™ Registers 110—DSL Mode 111—Power Down - 7 ...
Page 136
... This bit determines the Transmitter Clock Input Polarity. When written to a logical 1, the active edge on the SPTxClk input is the falling edge. When written to a logical 0, the active edge is the rising edge. Reserved, set to 0. Reserved, set to 0. Reserved, set to 0. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 137
... When written to a logical 1, this bit enables the Transmit DSS Scrambler. When written to a logical 0, the Transmit DSS Scrambler is disabled. When written to a logical 1, this bit enables the Receive DSS Scrambler. When written to a logical 0, the Receive DSS Scrambler is disabled. Mindspeed Technologies ™ Registers - ...
Page 138
... When written to a logical 1, this bit inserts a Cell Loss Priority (CLP) bit in the outgoing header from the TXHDR registers. When written to a logical 0, the CLP field is not changed prior to transmission. Description These bits hold the Transmit Idle Cell Payload values for outgoing idle cells. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 139
... When written to a logical 1, this bit disables Loss of Cell Delineation. When disabled, cells are passed even if cell delineation has not been found. When written to a logical 0, cells are passed only while cell alignment has been achieved. See Table 5-1. Mindspeed Technologies ™ Registers Table 5-1. ...
Page 140
... When written to a logical 1, this bit disables UTOPIA outputs for this port. Version CX28229-11 CX28229-12 and later These bits are the Multi-PHY Device Address. Each CX2822x port should have a unique address. These bits correspond to the URxAddr and UTxAddr pins. When the pin matches the bit values, the port is accessed. This port ignores any transactions meant for another port or PHY device ...
Page 141
... These bits hold the Transmit Header values for Octet 1 of the outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09). GFC/VPI bits (for UNI they are GFC bits, for NNI they are VPI bits) VPI bits Mindspeed Technologies ™ Registers - 7 ...
Page 142
... HDRFIELD register (0x09). VPI bits VCI bits Description These bits hold the Transmit Header values for Octet 3 of the outgoing cell. Insertion of the bits is controlled by the HDRFIELD register (0x09). VCI bits Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 143
... Cell Loss Priority bit Description These bits hold the Transmit Idle Cell Header values for Octet 1 of the outgoing cell. GFC/VPI bits (for UNI they are GFC bits, for NNI the are VPI bits) VPI bits Mindspeed Technologies ™ Registers - 7 43 ...
Page 144
... These bits hold the Transmit Idle Cell Header values for Octet 2 of the outgoing cell. VPI bits VCI bits Description These bits hold the Transmit Idle Cell Header values for Octet 3 of the outgoing cell. VCI bits Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 145
... These bits hold the Transmit Idle Cell Header values for Octet 4 of the outgoing cell. VCI bits Payload-type bits Cell Loss Priority bit Description These bits hold the Receive Header values for Octet 1 of the incoming cell. Mindspeed Technologies ™ Registers - 7 45 ...
Page 146
... RxHdr3[ RxHdr3[ RxHdr3[0] 7-46 Description These bits hold the Receive Header values for Octet 2 of the incoming cell. Description These bits hold the Receive Header values for Octet 3 of the incoming cell. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 147
... RxMsk1[ RxMsk1[ RxMsk1[ RxMsk1[0] 28229-DSH-001-D Description These bits hold the Receive Header values for Octet 4 of the incoming cell. Description These bits hold the Receive Header Mask for Octet 1 of the incoming cell. Mindspeed Technologies ™ Registers - 7 47 ...
Page 148
... RxMsk3[ RxMsk3[ RxMsk3[0] 7-48 Description These bits hold the Receive Header Mask for Octet 2 of the incoming cell. Description These bits hold the Receive Header Mask for Octet 3 of the incoming cell. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 149
... RxIdl1[ RxIdl1[ RxIdl1[0] 28229-DSH-001-D Description These bits hold the Receive Header Mask for Octet 4 of the incoming cell. Description These bits hold the Receive Idle cell header for Octet 1 of the incoming cell. Mindspeed Technologies ™ Registers - 7 49 ...
Page 150
... RxIdl3[ RxIdl3[0] 7-50 Description These bits hold the Receive Idle cell header for Octet 2 of the incoming cell. Description These bits hold the Receive Idle cell header for Octet 3 of the incoming cell. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 151
... IdlMsk1[ IdlMsk1[0] 28229-DSH-001-D Description These bits hold the Receive Idle cell header for Octet 4 of the incoming cell. Description These bits hold the Receive Idle cell header mask for Octet 1 of the incoming cell. Mindspeed Technologies ™ Registers - 7 51 ...
Page 152
... IdlMsk3[0] 7-52 Description These bits hold the Receive Idle cell header mask for Octet 2 of the incoming cell. Description These bits hold the Receive Idle cell header mask for Octet 3 of the incoming cell. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 153
... When written to a logical 1, this bit enables the Receive FIFO Overflow Interrupt. When written to a logical 1, this bit enables the Cell Sent Interrupt. Reserved for factory test, ignore. Reserved, set to a logical 0. Reserved, set to a logical 0. Mindspeed Technologies ™ Registers - 7 53 ...
Page 154
... When a logical 1 is read, this bit indicates that a Receive FIFO Overflow occurred. When a logical 1 is read, this bit indicates that a cell has been sent. Reserved for factory test, ignore. Reserved, set to a logical 0. Reserved, write to a logical 0. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 155
... When a logical 1 is read, this bit indicates that an Idle Cell has been received. When a logical 1 is read, this bit indicates that a Non-matching Cell has been received. When a logic 1 is read, this bit indicates that a Non-zero GFC has been received. Mindspeed Technologies ™ Registers - ...
Page 156
... When a logical 1 is read, this bit indicates that a cell has been rejected by the cell screening function. When a logical 1 is read, this bit indicates that a cell with a Non-zero GFC field in the header was received. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 157
... Received cell counter bit 0 (LSB). Description Received cell counter bit 15. Received cell counter bit 14. Received cell counter bit 13. Received cell counter bit 12. Received cell counter bit 11. Received cell counter bit 10. Received cell counter bit 9. Received cell counter bit 8. Mindspeed Technologies ™ Registers - 7 57 ...
Page 158
... LOCD Event counter bit 7 (MSB). LOCD Event counter bit 6. LOCD Event counter bit 5. LOCD Event counter bit 4. LOCD Event counter bit 3. LOCD Event counter bit 2. LOCD Event counter bit 1. LOCD Event counter bit 0 (LSB). Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 159
... Transmitted cell counter bit 0 (LSB). Description Transmitted cell counter bit 15. Transmitted cell counter bit 14. Transmitted cell counter bit 13. Transmitted cell counter bit 12. Transmitted cell counter bit 11. Transmitted cell counter bit 10. Transmitted cell counter bit 9. Transmitted cell counter bit 8. Mindspeed Technologies ™ Registers - 7 59 ...
Page 160
... Corrected HEC Error counter bit 6. Corrected HEC Error counter bit 5. Corrected HEC Error counter bit 4. Corrected HEC Error counter bit 3. Corrected HEC Error counter bit 2. Corrected HEC Error counter bit 1. Corrected HEC Error counter bit 0 (LSB). Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 161
... Received cell counter bit 0 (LSB). Description Received cell counter bit 15. Received cell counter bit 14. Received cell counter bit 13. Received cell counter bit 12. Received cell counter bit 11. Received cell counter bit 10. Received cell counter bit 9. Received cell counter bit 8. Mindspeed Technologies ™ Registers - 7 61 ...
Page 162
... Uncorrected HEC Error counter bit 6. Uncorrected HEC Error counter bit 5. Uncorrected HEC Error counter bit 4. Uncorrected HEC Error counter bit 3. Uncorrected HEC Error counter bit 2. Uncorrected HEC Error counter bit 1. Uncorrected HEC Error counter bit 0 (LSB). Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 163
... Non-matching cell counter bit 0 (LSB). Description Non-matching cell counter bit 15 (MSB). Non-matching cell counter bit 14. Non-matching cell counter bit 13. Non-matching cell counter bit 12. Non-matching cell counter bit 11. Non-matching cell counter bit 10. Non-matching cell counter bit 9. Non-matching cell counter bit 8. Mindspeed Technologies ™ Registers - 7 63 ...
Page 164
... The event occurs after the device has counted 8000 periods KHz clock. When set to 0, the OneSecIO pin is configured as an input. The one-second event must be genetared externally, by pulsing the OneSecIO pin for low-high-low. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 165
... When the ATM UTOPIA interface to TC block is enabled, (ATMmux[1:0] = "10"), this bit controls the bus width of the TC ATM-side UTOPIA interface. Reserved, set to zero. Reserved, set to zero. Reserved, set to zero. Description Reserved, set to zero. The value written into these bits will be asserted on the StatOut[1:0] output pins. Mindspeed Technologies ™ Registers - 7 65 ...
Page 166
... When set, this bit enables PortInt[3] to appear on the MicroInt* output. When set, this bit enables PortInt[2] to appear on the MicroInt* output. When set, this bit enables PortInt[1] to appear on the MicroInt* output. When set, this bit enables PortInt[0] to appear on the MicroInt* output. Mindspeed Technologies CX28224/5/9 Data Sheet Description Description ™ ...
Page 167
... Bit Default Name 7–4 pppp PartNum[3:0] 3–0 0001 Version[3:0] 28229-DSH-001-D Description Part number controlled by bondout: IMA2 – 0100 IMA4 – 0101 IMA8/32 – 1001 Version number of the device. 0001—Version -11 0010—Version -12 0011—Version -13 0100—Version -14 Mindspeed Technologies ™ Registers - 7 67 ...
Page 168
... Version Code II 3–0 Version Code III 7-68 Description 0x0 = CX28224, 2 ports 2 IMA groups 0x2 = CX28225, 4 ports 4 IMA groups 0x8 = CX28229, 32 ports 16 IMA groups 1 = Internal memory present 0x4 = CX2822x family major revision level Description 4 bit code: 0x2 = CX2822x-13 and earlier 0x3 = CX2822x-14 ...
Page 169
... This field has different ranges depending on Product type: CX28224: Unused, Set to 0 CX28225: Unused, Set to 0 CX28229: Range: 0–7 Description This bit is the current state of the signal ATMUTxAddr[4]. This bit is the current state of the signal ATMURxAddr[4]. ...
Page 170
... This field contains the least significant bits of the memory test address for the selected memory component. Range: 0x00–0xFF Description This field contains the middle significant bits of the memory test address for the selected memory component. Range: 0x00–0xFF Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 171
... This field contains the most significant bit of the SRAM write counter for the diagnostic link (selected using the field below). This field contains the PHY Cell Bus Address of the port for which a diagnostic measurement performed. Range: 0x00–0x1F Mindspeed Technologies ™ Registers - ...
Page 172
... All others (Range: 0x00–0xFF) Delay Window = 0 (see register 0x415): Value = Cell_count >> 1 Delay Window = 1–3 (see register 0x415): Value = Cell_count Delay Window = 4 (see register 0x415): Value = Cell_count >> 2 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 173
... Unexpected IMA Cell Offset condition of the ICP-INV anomaly was active sometime since the last time this register was read 0 = Unexpected IMA Cell Offset condition was inactive 1 = ICP-MIS anomaly was active sometime since the last time this register was read 0 = ICP-MIS defect was inactive Mindspeed Technologies ™ Registers - 7 ...
Page 174
... Exclusive OR of address bits from previous IMA core access. The number of bits in the exclusive OR operation is 10. Description An 8 bit register that can be written and read by the processor. The register is not used within the IMA Block. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 175
... Reserved. Set to 0. Reserved. Set to 0. For Multiplexer Type = 0, Multiplexer Type = 1, and Multiplexer Type = 3: CX28224: 0–1: IMA Group 1–2 CX28225: 0–3: IMA Group 1–4 CX28229: 0–0xF: IMA Group 1–16 For Multiplexer Type = 2: 0–1: Tx_TRL[0]–Tx_TRL[1] output Mindspeed Technologies ™ Registers ...
Page 176
... Use IMA_RefClk as source For Multiplexer Type 2 0x00–0x1F: Select timing from a Receive Port (see register 0x416) CX28224: 0–1: Port 0–1 CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 0x20: Use IMA_SysClk/24 0x21: Use IMA_RefClk as source 0x22: Use 8 kHz as source For Multiplexer Type 3 Reserved ...
Page 177
... The Gamma Value is the number of consecutive valid ICP cells needed for the link to enter the IMA Sync state. 28229-DSH-001-D Description Reserved. Set α α β β β β β γ γ γ γ γ Mindspeed Technologies ™ Registers - 7 77 ...
Page 178
... Reserved. Set Set Delay Threshold for an IMA group 1 = Set Delay Window for an IMA group Reserved. Set to 0. Reserved. Set to 0. CX28224: 0–1: IMA Group 1–2 CX28225: 0–3: IMA Group 1–4 CX28229: 0–0xF: IMA Group 1–16 Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 179
... Mindspeed Technologies ™ Registers - ...
Page 180
... For Control Type = Receive IMA Group 1 = Transmit IMA Group CX28224: 0–1: IMA Group 1–2 CX28225: 0–3: IMA Group 1–4 CX28229: 0–0xF: IMA Group 1–16 For Control Type = 6, 7 CX28224: 0–1: Port 0–1 CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 Mindspeed Technologies ™ ...
Page 181
... IMA group. The contents of this register are multiplied by 2048kbps in order to obtain the bandwidth. For Control Type = 6 This register contains the 8 lsbs of the payload bandwidth for the specific port of the Rx Timing clock synthesizer. The contents of this register are multiplied by 8kbps in order to obtain the bandwidth. Mindspeed Technologies ™ Registers - 7 81 ...
Page 182
... Description (Continued) For Control Type = 7 Reserved. Set to 0. This register contains the msb of the payload bandwidth for the specific port of the Rx Timing clock synthesizer. The contents of this register are multiplied by 2048kbps in order to obtain the bandwidth. Mindspeed Technologies ™ CX28224/5/9 Data Sheet 28229-DSH-001-D ...
Page 183
... Range 0x00–0x1F: Bypass Receive Port CX28224: 0–1: Port 0–1 CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 Range 0x20–0x2F: IMA Group CX28224: 0x20–0x21: IMA Group 1–2 CX28225: 0x20–0x23: IMA Group 1–4 CX28229: 0x20–0x2F: IMA Group 1–16 Mindspeed Technologies ™ Registers - 7 83 ...
Page 184
... CX28229: 0–0x1F: Port 0–31 Range 0x20–0x2F: IMA Group CX28224: 0x20–0x21: IMA Group 1–2 CX28225: 0x20–0x23: IMA Group 1–4 CX28229: 0x20–0x2F: IMA Group 1–16 0x30 All devices: ATM address is not assigned to this device For Translation Type = Internal Channel Active 0 = Internal Channel Inactive Don’ ...
Page 185
... Range 0x00–0x1F: Bypass Transmit Port CX28224: 0–1: Port 0–1 CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 Range 0x20–0x2F: IMA Group CX28224: 0x20–0x21: IMA Group 1–2 CX28225: 0x20–0x23: IMA Group 1–4 CX28229: 0x20–0x2F: IMA Group 1–16 Mindspeed Technologies ™ Registers - 7 85 ...
Page 186
... CX28229: 0–0x1F: Port 0–31 Range 0x20–0x2F: IMA Group CX28224: 0x20–0x21: IMA Group 1–2 CX28225: 0x20–0x23: IMA Group 1–4 CX28229: 0x20–0x2F: IMA Group 1–16 0x30 All devices: ATM address is not assigned to this device For Translation Type = Internal Channel Active 0 = Internal Channel Inactive Don’ ...
Page 187
... The read operation will clear the internal state. Reserved. Set to 0. Reserved. Set to 0. This field contains the PHY Cell Bus Address of the SOC being examined CX28224: 0–1: Port 0–1 CX28225: 0–3: Port 0–3 CX28229: 0–0x1F: Port 0–31 Mindspeed Technologies ™ Registers - 7 ...
Page 188
... CX28224) addresses 0x4D4–0x4D7 addresses 0x4D0–0x4D3 addresses 0x438–0x43F (Not defined for CX28224) addresses 0x430–0x437 (Not defined for CX28224) addresses 0x428–0x42F addresses 0x420–0x427 Mindspeed Technologies ™ CX28224/5/9 Data Sheet Description 28229-DSH-001-D ...
Page 189
... CX28224/5/9 Data Sheet 0x51F—IMA_GRP_5TO8_SEM (Group Table Control II (CX28229 Only)) For the following bits the group table is being updated the group table is not being updated. The update enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After writing to all 8 elements, the update enable is reset to 0 ...
Page 190
... Registers 0x61F—IMA_GRP_9TO12_SEM (Group Table Control III (CX28229 Only)) For the following bits the group table is being updated the group table is not being updated. The update enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After writing to all 8 elements, the update enable is reset to 0 ...
Page 191
... CX28224/5/9 Data Sheet 0x71F—IMA_GRP_13TO16_SEM (Group Table Control IV (CX28229 Only)) For the following bits the group table is being updated the group table is not being updated. The update enable must be set to 1 prior to writing the group table. All elements of the group table must be re-written. After writing to all 8 elements, the update enable is reset to 0 ...
Page 192
... Not Applicable Not Applicable CX28229 Description In support of the Test Pattern Procedure, this field is set equal to the value acquired from the Receive side test link. See address 0x4E7. When the Test Pattern Procedure is inactive, the Rx Test Pattern field should be set to 0xFF. Range: 0x00–0xFF Mindspeed Technologies ™ ...
Page 193
... Not Applicable Not Applicable CX28229 Description 1 = Group is established and a round-robin is created 0 = Group is not established 1 = certain LSM transitions (Unusable → Usable, Usable → Active) are allowed 0 = certain LSM transitions (Unusable → Usable, Usable → Active) are blocked Reserved. Set Group is inhibited from carrying traffic 0 = Group is not inhibited Reserved ...
Page 194
... Reserved. Set to 0. Reserved. Set to 0. IMA OAM Label value 1 = IMA v1 IMA v1.0 This field contains the PHY port address of the Transmit link with the lowest LID in the group. CX28224: Range: 0–1 CX28225: Range: 0–3 CX28229: Range: 0–0x1F Mindspeed Technologies ™ CX28224/5/9 Data Sheet n=11 n=12 n=13 n=14 n=15 ...
Page 195
... CX28224 CX28225 Bit Default Name 7–0 0x00 Tx Group ID 28229-DSH-001-D n=6 n=7 n=8 n=9 n=10 Not Applicable Not Applicable CX28229 Description This field contains the Transmit Group ID sent in the Transmit ICP cells of all links within the group. Range: 0x00–0xFF Mindspeed Technologies ™ Registers n=11 n=12 n=13 n=14 n=15 n= ...
Page 196
... Group Symmetry 1–0 0 Frame Length (M) 7-96 n=6 n=7 n=8 n=9 n=10 Not Applicable Not Applicable CX28229 Description 0 = Start- Start-up-Ack 2 = Config-Abort–Unsupported Config-Abort–Incompatible Symmetry 4 = Config-Abort–Unsupported IMA Version 5–7 = Reserved for other Config-Abort states 8 = Insufficient Links 9 = Blocked 0xA = Operational 0xB–F = reserved 0 = Symmetrical configuration and operation ...
Page 197
... Link ID 28229-DSH-001-D n=6 n=7 n=8 n=9 n=10 Not Applicable Not Applicable CX28229 Description Unused: Set to 0. Unused: Set Independent Transmit Clock (ITC Common Transmit Clock (CTC) Unused: Set to 0. Unused: Set to 0. This field contains the LID of the Transmit TRL. Range: 0x0–0x7 Mindspeed Technologies ™ ...
Page 198
... Not Applicable Not Applicable CX28229 Description If the Test Link Command is set to Active, the Tx Test Pattern is sent in the ICP cell of the Transmit Test Link. For other links and when the Test Link Command is Inactive, the Tx Test Pattern in the Transmit ICP cells will automatically be set to 0x00. Range: 0x00– ...
Page 199
... Not Applicable Not Applicable CX28229 Transmit Group Cell Count: This field contains the most significant bits bit count of the number of ATM layer cells transmitted over the Transmit links within the group. A write operation to the first address (0x440 for Group #1, 0x442 for Group #2, 0x01 etc ...
Page 200
... Not Applicable Not Applicable CX28229 Receive Group Cell Count: This field contains the most significant bits bit count of the number of ATM layer cells received over the Receive links within the group. A write operation with data = 0x01 to the first address (0x450 for Group #1, 0x452 for Group #2, etc ...