EM6A9320BI-5MG Etron Technology Inc., EM6A9320BI-5MG Datasheet
EM6A9320BI-5MG
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EM6A9320BI-5MG Summary of contents
Page 1
... VDD = 2.5V ± 5% VDDQ = 2.5V ± 5% • Interface : SSTL_2 I/O compatible • Package: 144-ball TFBGA -Pb free Table1. Ordering Information Part Number Clock Frequency EM6A9320BI-5MG BI: indicates TFBGA package M : indicates in the last digit: indicates 0.11um process generation G: ndicates Pb Free for TFBGA Package i Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. ...
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... D10 VDDQ A2 VDD K3 VDDQ G11 VDD K6 VDDQ G2 VDD K7 VSS A11 VDD K10 VSS M3 VDDQ B2 VSS L4 VDDQ B4 VSS 2 EM6A9320BI DQ29 DQ28 VSSQ DM3 DQ30 VDDQ NC VDDQ VSSQ VSSQ VSSQ DQ26 VSSQ VSS VDD VDDQ VSS VSSQ VDDQ DQ15 VSS VSSQ ...
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... DQ0 DQ31 Etron Confidential 4Mx32 bit DDR SDRAM CONTROL SIGNAL GENERATOR MODE REGISTER DQ Buffer DM0~3 3 EM6A9320BI 4096 x 256 x 32 CELL ARRAY (BANK #0) Column Decoder 4096 x 256 x 32 CELL ARRAY (BANK #1) Column Decoder 4096 x 256 x 32 CELL ARRAY (BANK #2) Column Decoder 4096 x 256 x 32 ...
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... Data I/O: The DQ0-DQ31 input and output data are synchronized with the positive DQ0 - DQ31 Input / Output edges of CK and CK . The I/Os are byte-maskable during Writes. V Supply Power Supply: Power for the input buffers and core logic DD Etron Confidential 4Mx32 bit DDR SDRAM Table 3. Pin Details of EM6A9320 Description 4 EM6A9320BI . Rev 1.2 Feb. 2008 ...
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... No Connect: These pins should be left unconnected Note: The timing reference point for the differential clocking is the cross point of the CK and CK . For any applications using the single ended clocking, apply V Etron Confidential 4Mx32 bit DDR SDRAM . DDQ to CK pin. REF 5 EM6A9320BI Rev 1.2 Feb. 2008 ...
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... ( ( EM6A9320BI A8 A11-A9, A7-0 CS RAS V Row Address Column Address A0~ ...
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... Etron Confidential 4Mx32 bit DDR SDRAM A1 A0 Burst Length 0 0 Reserved Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved Addressing Mode Sequential Interleave n+1 n+2 n+3 2 words 4 words 8 words 7 EM6A9320BI n+4 n+5 n+6 n+7 Rev 1.2 Feb. 2008 ...
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... CAS Latency 0 0 Reserved 0 1 Reserved 1 0 Reserved Reserved 0 1 Reserved 1 0 Reserved 1 1 Reserved Test Mode Normal mode DLL Reset Test mode MRS Cycle 1 Extended Functions (EMRS) 8 EM6A9320BI Burst Length A0 A0# 4 words 8 words A0 A0# 3 clocks Rev 1.2 Feb. 2008 ...
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... WRIDOFF Etron Confidential 4Mx32 bit DDR SDRAM DS1 Strength Full 100% 60% RFU RFU Do not use Output driver matches impedance 30% 9 EM6A9320BI RFU must be set to “0” Comment Rev 1 DS0 DLL A0 DLL Enable 0 1 Disable Feb. 2008 ...
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... REF V + 0.15 - REF Vssq - 0 0. (VDD = 2.5 V ± 5 1MHz ° C) Parameter DM, Input Capacitance and and V DDQ SSQ 10 EM6A9320BI Rating Unit Note -5 +0 DDQ V 1 0~70 ° ° 260 ° 2 (SSTL_2 In/Out ° C) Max. Unit Note 2 ...
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... Address and CK CK (min) =t (min (min) RC RFC and t . Input signals are changed one time during EM6A9320BI (VDD=2.5V ± 5%,Ta=0~70 ° Symbol MAX (min); IDD0 210 IDD1 240 IDD2P 75 IDD2N 100 IDD3P 75 IDD3N 220 IDD4R 420 IDD4W ...
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... Etron Confidential 4Mx32 bit DDR SDRAM -5 Min 0.45 0. 0.9 0.4 0.8 0 0.25 0.4 0.4 0.4 1.0 1.0 0.5 0.5 tCLMIN or tCHMIN - tHP - tQHS 200 tIS + 2tCK - - - 12 EM6A9320BI Unit Max 10 ns 0.55 tCK 0.55 tCK 1.4 ns 1.4 ns 0.4 ns 1.1 tCK 0.6 tCK 1.2 tCK - tCK - tCK 0.6 tCK 0.6 tCK 0.6 tCK - 0 ...
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... REF IH V (AC (AC) 0 (AC) 0.5*V DDQ Input signals are changed one time during t ) RFE Reference to the Test Load Figure 3. SSTL_2 A.C. Test Load 0.5 x VDDQ DQ, DQS Z0=50Ω 13 EM6A9320BI (Ta = 0~70 °C, VDD=2.5 ± Max. + 0.4 V – 0.4 REF V 0.6 DDQ + -0.2 0.5*V +0.2 DDQ . CK 0 DDQ V +0 -0.4 V REF REF 1 V/ns 0 DDQ 50Ω ...
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... Issue MRS – reset DLL. (An additional 200 clock cycles are required to lock the DLL). 7) Precharge all banks of the device. 8) Issue two or more Auto Refresh commands. 9) Issue MRS – with A8 to low to initialize the mode register. Etron Confidential 4Mx32 bit DDR SDRAM V and V DDQ, TT REF 14 EM6A9320BI when all input signals are held Rev 1.2 Feb. 2008 ...
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... Timing Waveforms Figure 4. Activating a Specific Row in a Specific Bank CK CK CKE HIGH CS RAS CAS WE RA Address BA BA0,1 Etron Confidential 4Mx32 bit DDR SDRAM RA=Row Address BA=Bank Address Don’t Care 15 EM6A9320BI Rev 1.2 Feb. 2008 ...
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... DIS AP BA0,1 BA CA=Column Address BA=Bank Address EN AP=Enable Autoprecharge DIS AP=Disable Autoprecharge Etron Confidential 4Mx32 bit DDR SDRAM NOP ACT Row Bank B t RRD Don’t Care 16 EM6A9320BI RD/W NOP NOP R Col Bank B t RCD Don’t Care Rev 1.2 NOP Feb. 2008 ...
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... DO n=Data Out from column n Burst Length=4 3 subsequent elements of Data Out appear in the programmed order following DO n Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP NOP CL=2 NOP NOP NOP CL=3 17 EM6A9320BI NOP NOP Don’t Care NOP NOP DO n Don’t Care Rev 1.2 Feb. 2008 ...
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... Read commands shown must be to the same device Etron Confidential 4Mx32 bit DDR SDRAM NOP READ NOP Bank, Col o CL=2 NOP READ NOP Bank, Col o CL=3 18 EM6A9320BI NOP NOP DO o Don’t Care NOP NOP Don’t Care Rev 1.2 Feb. 2008 ...
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... Data Out appear in the programmed order following DO n (and following DO o) Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP READ Bank, Col o CL=2 REA NOP NOP D Bank, Col o CL EM6A9320BI NOP NOP NOP DO o Don’t Care NOP NOP NOP DO o Don’t Care Rev 1.2 Feb. 2008 ...
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... DDR SDRAM READ READ READ Bank, Bank, Bank, Col o Col p Col q CL=2 READ READ READ Bank, Bank, Bank, Col o Col p Col q CL=3 20 EM6A9320BI NOP NOP Don’t Care NOP NOP Don’ ...
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... Cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of Data Out appear in the programmed order following DO n Etron Confidential 4Mx32 bit DDR SDRAM NOP BST NOP CL=2 NOP BST NOP CL=3 21 EM6A9320BI NOP NOP Don’t Care NOP NOP DO n Don’t Care Rev 1.2 Feb. 2008 ...
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... Data Out appears in the programmed order following DO n Data in elements are applied following the programmed order Etron Confidential 4Mx32 bit DDR SDRAM BST NOP NOP CL=2 EM6A9320BI NOP WRITE Bank, Col o tDQSS min DI o Don’t Care Rev 1.2 ...
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... Burst Length the cases shown (applies for bursts well; if burst length is 2, the BST command shown can be NOP) 1 subsequent element of Data Out appears in the programmed order following DO n Data in elements are applied following the programmed order Etron Confidential 4Mx32 bit DDR SDRAM BST NOP NOP CL=3 23 EM6A9320BI NOP WRITE Bank, Col o tDQSS min Don’ ...
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... Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met Etron Confidential 4Mx32 bit DDR SDRAM NOP PRE NOP Bank (a or all) CL=2 EM6A9320BI NOP ACT t RP Bank A, Row Don’t Care Rev 1.2 Feb. 2008 ...
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... Note that Precharge may not be issued before tRAS ns after the ACTIVE command for applicable banks The Active command may be applied if tRC has been met Etron Confidential 4Mx32 bit DDR SDRAM NOP PRE NOP Bank (a or all) CL=3 25 EM6A9320BI NOP ACT t RP Bank A, Row DO n Don’t Care Rev 1.2 Feb. 2008 ...
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... Figure 14. Write Command CK CK CKE HIGH CS RAS CAS DIS AP BA0,1 BA CA=Column Address BA=Bank Address EN AP=Enable Autoprecharge DIS AP=Disable Autoprecharge Etron Confidential 4Mx32 bit DDR SDRAM Don’t Care 26 EM6A9320BI Rev 1.2 Feb. 2008 ...
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... Data In are applied in the programmed order following non-interrupted burst shown A8 is LOW with the WRITE command (AUTO PRECHARGE disabled) Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP tDQSS max EM6A9320BI T6 T7 NOP Don’t Care Rev 1.2 Feb. 2008 ...
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... Data In are applied in the programmed order following non-interrupted burst shown A8 is LOW with the WRITE command (AUTO PRECHARGE disabled) Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP EM6A9320BI T6 NOP Don’t Care Rev 1.2 Feb. 2008 ...
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... A non-interrupted burst shown A8 is LOW with the WRITE command (AUTO PRECHARGE disabled) DM=DM0 ~ DM3 Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP NOP EM6A9320BI T10 T11 NOP NOP Don’t Care Rev 1.2 Feb. 2008 ...
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... Data In are applied in the programmed order following DI o Non-interrupted bursts of 4 are shown DM= DM0 ~ DM3 Etron Confidential 4Mx32 bit DDR SDRAM NOP WRITE NOP Bank , Col EM6A9320BI T10 T11 NOP NOP DI o Don’t Care Rev 1.2 Feb. 2008 ...
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... Data In are applied in the programmed order following DI o Non-interrupted bursts of 4 are shown DM= DM0 ~ DM3 Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP WRITE Bank Col EM6A9320BI T8 T9 T10 T11 T7 NOP NOP DI n Don’t Care Rev 1.2 Feb. 2008 ...
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... Each WRITE command may be to any bank and may be to the same or different devices DM= DM0 ~ DM3 Etron Confidential 4Mx32 bit DDR SDRAM WRITE WRITE Bank Bank Col o Col EM6A9320BI WRITE WRITE Bank Bank Col r Col Don’t Care Rev 1 ...
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... The READ and WRITE commands are to the same devices but not necessarily to the same bank DM= DM0 ~ DM3 Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP NOP EM6A9320BI T10 T11 NOP READ tWTR Bank Col o CL=2.5 Don’t Care Rev 1.2 Feb. 2008 ...
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... The READ and WRITE commands are to the same devices but not necessarily to the same bank DM= DM0 ~ DM3 Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP NOP EM6A9320BI T8 T9 T10 T7 NOP READ tWTR Bank Col o CL=2.5 Don’t Care Rev 1.2 Feb. 2008 T11 ...
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... The READ and WRITE commands are to the same devices but not necessarily to the same bank DM= DM0~ DM3 Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP NOP tWTR EM6A9320BI T10 T11 NOP READ Bank Col o CL=2.5 Don’t Care Rev 1.2 Feb. 2008 ...
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... CK edge after the last Data In Pair A8 is LOW with the WRITE command (AUTO PRECHARGE is disabled) DM= DM0 ~ DM3 Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP NOP EM6A9320BI T10 T11 NOP PRE tWTR Bank (a or al) tRP Don’t Care Rev 1.2 Feb. 2008 ...
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... DQS becomes don't care at this point DM DM3 Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP NOP EM6A9320BI T8 T9 T10 T7 PRE NOP tWTR Bank (a or all) tRP * Don’ ...
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... DQS becomes don't care at this point DM= DM0 ~ DM3 Etron Confidential 4Mx32 bit DDR SDRAM NOP NOP NOP EM6A9320BI T8 T9 T10 T7 PRE NOP tWTR Bank (a or all) tRP * Don’ ...
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... Figure 27. Precharge Command CK CK CKE HIGH CS RAS CAS WE A0-A7, A9-A11 ALL BANKS A8 ONE BANK BA0,1 BA BA= Bank Address ( LOW, otherwise don't care) Don’t Care Etron Confidential 4Mx32 bit DDR SDRAM 39 EM6A9320BI Rev 1.2 Feb. 2008 ...
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... Etron Confidential 4Mx32 bit DDR SDRAM Tn+1 Tn NOP Enter power-down mode T4 Tx Tx+1 Ty Frequency Change Occurs here Stable new clock Before power down exit 40 EM6A9320BI Tn+3 Tn+4 Tn+5 Tn NOP VALID Exit power-down mode Don’t Care Ty+1 Ty+2 Ty+3 Ty+4 DLL NOP NOP NOP RESET t IS 200 Clocks Rev 1 ...
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... Figure 31. Data Output (Read) Timing DQS DQ t DQSQ max Burst Length = 4 in the case shown Etron Confidential 4Mx32 bit DDR SDRAM t t DQSH DQSL DQSQ max EM6A9320BI Don’t Care Rev 1.2 Feb. 2008 ...
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... BA0=H BA0=L BA1=L BA1=L **t **t MRD MRD Extended mode Load Mode Register set Register, Reset DLL (with A8=H) 42 EM6A9320BI AR AR MRS CODE CODE t IH BA0=L BA1 **t RP RFC RFC 200 cycles of CK** Load Mode Register, (with A8=L) Don’t Care Rev 1 ...
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... Precharge Power Down. If this command is an ACTIVE ( least one row is already active) then the Power-Down mode shown is active Power Down. Etron Confidential 4Mx32 bit DDR SDRAM NOP Enter power-down mode 43 EM6A9320BI t IS NOP VALID VALID Exit power-down mode Don’t Care Rev 1.2 Feb. 2008 ...
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... DM, DQ and DQS signals are all Etron Confidential 4Mx32 bit DDR SDRAM VALID NOP AR NOP NOP t RP Don't Care /High-Z for operations shown 44 EM6A9320BI VALID AR NOP NOP t t RFC RFC Don’t Care Rev 1.2 ACT Feb. 2008 ...
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... Etron Confidential 4Mx32 bit DDR SDRAM Clock must be stable before Exiting Self Refresh mode Enter Self Refresh mode All banks idle state prior to entering Self Refresh mode 45 EM6A9320BI t IS NOP VALID VALID t XSNR/ t XSRD** Exit Self Refresh mode Don’ ...
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... RPST t RPRE t LZ min min min t DQSCK t max RPST t RPRE t LZ max max max 46 EM6A9320BI t IH VALID VALID ACT NOP NOP NOP Bank max Don’t Care Rev 1.2 VALID NOP Feb. 2008 ...
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... RPST t RPRE t LZ min min min t DQSCK t RPST max t RPRE t LZ max max max (BL*tCK/2) 47 EM6A9320BI t IH VALID VALID NOP ACT NOP NOP Bank max Don’t Care Rev 1.2 VALID NOP Feb. 2008 ...
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... CL NOP NOP READ NOP Col DIS AP Bank RAS CL=3 t RPRE t LZ min t LZ max 48 EM6A9320BI NOP PRE NOP NOP ACT RA RA ALL BANKS RA ONE BANKS Bank X *Bank DQSCK t min RPST min min ...
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... NOP NOP NOP NOP t t DSH DSH t t DQSH WPST t DQSL t WPRE DSS t DSS t DQSH DQSS t WPST t DQSL EM6A9320BI VALID PRE NOP NOP ALL BANKS ONE BANKS *Bank Don’t Care Rev 1.2 ACT Feb. 2008 ...
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... DDR SDRAM VALID NOP NOP NOP NOP t DSH t DSH t t DQSH WPST t DQSL DSS t DSS t DQSH DQSS t WPST t DQSL EM6A9320BI VALID VALID NOP NOP NOP ACT DAL Don’t Care Rev 1.2 Feb. 2008 ...
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... IS IH DIS AP Bank X t RAS t RCD t DSH t t DQSH DQSS t WPRES t WPRE DQSS t WPRES t WPRE 51 EM6A9320BI NOP NOP NOP DSH t WPST t DQSL t DSS t t DSS DQSH t WPST t DQSL DI n Don’t Care Rev 1.2 PRE ALL BANKS ONE BANK *Bank X Feb ...
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... CH CL NOP NOP NOP NOP t DSH t DSH t t DQSH WPST t DQSL t WPRE DSS t DSS t DQSH DQSS t WPST t DQSL EM6A9320BI VALID NOP NOP PRE ALL BANKS ONE BANKS *Bank Don’t Care Rev 1.2 ACT Feb. 2008 ...
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... SEATING PLANE Etron Confidential 4Mx32 bit DDR SDRAM 0.08 0.15 0.40~0.50 (144X 1. 0.15 (4x) C Ball pitch : 0.80 Ball Diam eter : 0.45 0. EM6A9320BI BOTTOM VIEW PIN A1 CORNER 0.80 8.80 Rev 1.2 Feb. 2008 ...