EM638165TS-7G Etron Technology Inc., EM638165TS-7G Datasheet

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EM638165TS-7G

Manufacturer Part Number
EM638165TS-7G
Description
Manufacturer
Etron Technology Inc.
Datasheet

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Etron Confidential
Features
• Fast access time from clock: 4.5/5/5.4 ns
• Fast clock rate: 200/166/143 MHz
• Fully synchronous operation
• Internal pipelined architecture
• 1M word x 16-bit x 4-bank
• Programmable Mode registers
• Auto Refresh and Self Refresh
• 4096 refresh cycles/64ms
• CKE power down mode
• Single +3.3V ± 0.3V power supply
• Interface: LVTTL
• 54-pin 400 mil plastic TSOP II package
• 60-ball 6.4mm x 10.1mm VFBGA package
Key Specifications
tCK3 Clock Cycle time(min.)
tAC3 Access time from CLK(max.)
tRAS Row Active time(min.)
tRC
Ordering Information
TS: indicates TSOPII Package,
VE: indicates VFBGA Package,
G: indicates Pb and Halogen Free for TSOPII Package
Etron Technology, Inc.
No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C.
TEL: (886)-3-5782345
Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice.
EM638165TS/VE-5G
EM638165TS/VE-6G
EM638165TS/VE-7G
- CAS Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
- Pb free and Halogen free
- Pb free
Indicates Pb Free for VFBGA Package
Part Number
Row Cycle time(min.)
EM638165
Frequency
200MHz
166MHz
143MHz
FAX: (886)-3-5778671
4M x 16 bit Synchronous DRAM (SDRAM)
TSOP II, VFBGA
TSOP II, VFBGA
TSOP II, VFBGA
4.5/5/5.4 ns
35/42/45 ns
50/60/63 ns
Package
5/6/7 ns
- 5/6/7
Overview
CMOS synchronous DRAM containing 64 Mbits. It
is internally configured as 4 Banks of 1M word x 16
DRAM with a synchronous interface (all signals are
registered on the positive edge of the clock signal,
CLK). Read and write accesses to the SDRAM are
burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with
the registration of a BankActivate command which
is then followed by a Read or Write command.
Read or Write burst lengths of 1, 2, 4, 8, or full page,
with a burst termination option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. The refresh functions, either Auto or Self
Refresh
programmable mode register, the system can
choose the most suitable modes to maximize its
performance. These devices are well suited for
applications requiring high memory bandwidth and
particularly well suited to high performance PC
applications.
The EM638165 SDRAM is a high-speed
The EM638165 provides for programmable
are
easy
to
(Rev 2.0, Mar./2008)
use.
EM638165
By
having
a

Related parts for EM638165TS-7G

EM638165TS-7G Summary of contents

Page 1

... Ordering Information Part Number Frequency EM638165TS/VE-5G 200MHz EM638165TS/VE-6G 166MHz EM638165TS/VE-7G 143MHz TS: indicates TSOPII Package, VE: indicates VFBGA Package, G: indicates Pb and Halogen Free for TSOPII Package Indicates Pb Free for VFBGA Package Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. ...

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Pin Assignment (TSOP II Top View) 1 VDD 2 DQ0 3 VDDQ 4 DQ1 DQ2 5 VSSQ 6 DQ3 7 DQ4 8 VDDQ 9 DQ5 10 DQ6 11 VSSQ 12 DQ7 13 VDD 14 LDQM 15 WE# 16 CAS# 17 ...

Page 3

Block Diagram CLOCK CLK BUFFER CKE CS# RAS# COMMAND DECODER CAS# WE# COLUMN A10/AP COUNTER A0 ADDRESS A9 BUFFER A11 BA0 BA1 REFRESH COUNTER Etron Confidential CONTROL SIGNAL GENERATOR MODE REGISTER 3 EM638165 CELL ARRAY (BANK #A) ...

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Pin Descriptions Symbol Type CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input ...

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LDQM, Input Data Input/Output Mask: Controls output buffers in read mode and masks UDQM Input data in write mode. DQ0-DQ15 Input / Data I/O: The DQ0-15 input and output data are synchronized with the positive Output edges of CLK. The ...

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Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Command BankActivate BankPrecharge PrechargeAll Write Write and AutoPrecharge Read Read and Autoprecharge Mode ...

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Commands 1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address) The BankActivate command activates the idle bank designated by the BA0, 1 signal. By latching the row address ...

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T0 T1 CLK READ A NOP COMMAND CAS# latency=2 ’ CK2, CAS# latency=3 ’ CK3, Burst Read Operation The read data appears on the DQs subject to the values on the DQM inputs two ...

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T0 T1 CLK DQM COMMAND NOP READ A ’ Read to Write Interval T0 CLK DQM COMMAND NOP CAS# latency=2 ’ CK2, Read to Write Interval A read burst without the auto precharge function may ...

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Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A7 = Column Address) The Read and AutoPrecharge command automatically performs the precharge operation after the read operation. Once this ...

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T0 CLK COMMAND NOP WRITE A CAS# latency=2 ’ CK2, CAS# latency=3 ’ CK3, Input data for the write is masked Write Interrupted by a Read The BankPrecharge/PrechargeAll command that interrupts a write burst ...

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T0 CLK Bank A COMMAND Activate CAS# latency=2,3 ’ CK DAL WR Burst Write with Auto-Precharge 8 Mode Register Set command (RAS# = "L", CAS# = "L", WE# = "L", A0-A11 = Register Data) ...

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The mode register is divided into various fields depending on functionality. Address BA0,1 A11,10 Function RFU* RFU* *Note: RFU (Reserved for future use) should stay “0” during MRS cycle. • Burst Length Field (A2~A0) This field specifies the data length ...

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CAS# Latency Field (A6~A4) This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS# Latency depends on the frequency of CLK. The minimum ...

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T0 CLK NOP COMMAND CAS# latency=2,3 ’ CK1, Termination of a Burst Write Operation 11 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address ...

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Clock Suspend Mode Exit / PowerDown Mode Exit command (CKE= "H") When the internal CLK has been suspended, the operation of the internal CLK is reinitiated from the subsequent cycle by providing this command (asserting CKE "HIGH", the command ...

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Absolute Maximum Rating Symbol Input, Output Voltage IN OUT Power Supply Voltage DD DDQ T Ambient Temperature A T Storage Temperature STG T Soldering Temperature (10 second) SOLDER P Power Dissipation D I Short ...

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Recommended D.C. Operating Conditions Description/Test condition Operating Current ≥ (min), Outputs Open RC RC One bank active Precharge Standby Current in non-power down mode = 15ns, CS# ≥ V (min), CKE ≥ Input signals ...

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Electrical Characteristics and Recommended A.C. Operating Conditions = 3.3V ± 0.3V 0~70°C) (Note Symbol A.C. Parameter t Row cycle time RC (same bank) t RAS# to CAS# delay RCD (same bank) ...

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A.C. Test Conditions LVTTL Interface Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals 1.2kΩ Output 30pF LVTTL D.C. Test Load (A) 7. Transition times ...

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Timing Waveforms Figure 1. AC Parameters for Write Timing T10 CLK CKE CS# RAS# CAS# WE# BA0,1 t ...

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Figure 2. AC Parameters for Read Timing CLK CKE t IS CS# RAS# CAS# WE# BA0,1 A10 RAx t IS A0-A9, RAx A11 DQM Hi-Z DQ Activate Command Bank A Etron Confidential ...

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Figure 3. Auto Refresh (CBR T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 A0-A9, A11 t RP DQM DQ Precharge All Auto Refresh Command Command Etron Confidential ...

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Figure 4. Power on Sequence and Auto Refresh (CBR T10 CLK t CK CKE High Level is reauired CS# RAS# CAS# WE# BA0,1 A10 Address Key A0-A9, A11 DQM t ...

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Figure 5. Self Refresh Entry & Exit Cycle CLK *Note 2 *Note 1 CKE t IS CS# *Note 8 RAS# CAS# BA0,1 A0-A9, A11 WE# DQM Hi-Z DQ Self Refresh Enter Note: To Enter SelfRefresh ...

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Figure 6.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx CAx A11 DQM ...

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Figure 6.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx CAx A11 DQM ...

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Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx CAx A11 DQM ...

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Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx CAx A11 DQM ...

Page 30

Figure 8. Power Down Mode and Clock Mask T10 CLK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx A11 DQM Hi-Z DQ ...

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Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAw A0-A9, RAw CAw A11 ...

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Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAw A0-A9, RAw CAw A11 ...

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Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBw A0-A9, RBw CBw A11 ...

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Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBw A0-A9, RBw CBw A11 ...

Page 35

Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RBx A0-A9, RBx CBx A11 t t ...

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Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RBx A0-A9, CBx RBx A11 t RCD ...

Page 37

Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx CAx A11 t RCD ...

Page 38

Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx CAx A11 t RCD ...

Page 39

Figure 13.1. Read and Write Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx A0-A9, RAx CAx A11 DQM Hi-Z DQ Ax0 Activate Read Cammand ...

Page 40

Figure 13.2. Read and Write Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx A0-A9, RAx CAx A11 DQM Hi-Z DQ Activate Read Cammand Command ...

Page 41

Figure 14.1. Interleaving Column Read Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx RAx A0-A9, RAx CAy RAx A11 RCD DQM ...

Page 42

Figure 14.2. Interleaved Column Read Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RBx RAx RAx A0-A9, RAx CAx RBx A11 t RCD DQM Hi-Z DQ ...

Page 43

Figure 15.1. Interleaved Column Write Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBw RAx A0-A9, RAx CAx RBw A11 t RCD DQM t RRD ...

Page 44

Figure 15.2. Interleaved Column Write Cycle T10 CLK t CK CKE CS# RAS# CAS# WE# BA0.1 A10 RAx RBw RAx A0-A9, RAx CAx RBw A11 t RCD DQM t >t ...

Page 45

Figure 16.1. Auto Precharge after Read Burst T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx RBx A0-A9, RAx CAx RBx A11 DQM Hi-Z DQ ...

Page 46

Figure 16.2. Auto Precharge after Read Burst T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx RBx A0-A9, RAx CAx RBx A11 DQM Hi-Z DQ ...

Page 47

Figure 17.1. Auto Precharge after Write Burst T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx RBx A0-A9, RAx CAx RBx A11 DQM Hi-Z DQ ...

Page 48

Figure 17.2. Auto Precharge after Write Burst T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx RBx A0-A9, RAx CAx RBx A11 DQM Hi-Z DQ ...

Page 49

Figure 18.1. Full Page Read Cycle T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBx A0-A9, RAx CAx RBx A11 DQM Hi Activate ...

Page 50

Figure 18.2. Full Page Read Cycle T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBx A0-A9, RAx CAx RBx A11 DQM Hi-Z DQ Activate Read ...

Page 51

Figure 19.1. Full Page Write Cycle T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBx A0-A9, RAx CAx RBx A11 DQM Hi-Z DQ DAx DAx+1 ...

Page 52

Figure 19.2. Full Page Write Cycle T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBx A0-A9, RAx CAx RBx A11 DQM Hi-Z DQ DAx DAx+1 ...

Page 53

Figure 20. Byte Write Operation T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx CAx A11 LDQM UDQM DQ0-DQ7 Ax0 DQ8-DQ15 Activate Read Upper ...

Page 54

Figure 21. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency= T10 CLK t CK High CKE Begin Auto Begin Auto Precharge Precharge Bank B Bank A CS# RAS# CAS# ...

Page 55

Figure 22. Full Page Random Column Read T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RAx RBx A0-A9, RAx RBx CAx A11 DQM t t RCD ...

Page 56

Figure 23. Full Page Random Column Write T10 CLK t CK CKE CS# RAS# CAS# WE# BA0,1 A10 RAx RBx RAx A0-A9, RAx RBx CAx CBx A11 DQM t t ...

Page 57

Figure 24. Precharge Termination of a Burst (Burst Length= Full Page, CAS# Latency= T10 CLK t CK High CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9, RAx ...

Page 58

Pin TSOP II Package Outline Drawing Information Dimension in inch Symbol Min Nom A --- A1 0.002 A2 0.035 0.039 B 0.01 0.014 C 0.004 0.006 D 0.87 0.875 E 0.395 0.400 e --- 0.031 HE 0.455 0.463 L ...

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Units in mm TOP VIEW A1 CORNER SEATING PLANE Etron Confidential 0.10(4X) ...

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