GL811E Genesys Logic, GL811E Datasheet

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GL811E

Manufacturer Part Number
GL811E
Description
Manufacturer
Genesys Logic
Datasheet

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Genesys Logic, Inc.
GL811E
USB 2.0 to ATA / ATAPI
Bridge Controller
Datasheet
Revision 1.25
May. 03, 2006

Related parts for GL811E

GL811E Summary of contents

Page 1

... Genesys Logic, Inc. GL811E USB 2.0 to ATA / ATAPI Bridge Controller Datasheet Revision 1.25 May. 03, 2006 ...

Page 2

... All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http ://www.genesyslogic.com ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Page 2 ...

Page 3

... GL811E USB 2.0 to ATA/ATAPI Bridge Controller Revision History Description First formal release. Changed product name from GL811 to GL811E. 1. Added some features in Chapter 2. 2. Added 64 pin LQFP data in pinouts, pin description and package dimension. 3. Added Chapter 8 “Ordering Infromation”. Changed pin# 38,39,21 name from IOADR0~2 to DA0~2. ...

Page 4

... Switching Characteristics ............................................................ 16 6 HARACTERISTICS 6.4.1 Register Transfers ........................................................................ 18 6.4.2 Multiword DMA data transfer .................................................... 19 6.4.3 Ultra DMA data transfer ............................................................. 23 6 HARACTERISTICS CHAPTER 7 PACKAGE DIMENSION................................................... 31 CHAPTER 8 ORDERING INFORMATION........................................... 33 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller TABLE OF CONTENTS ................................................................................ 11 R ............................................................ 15 ATINGS ................................................................. 15 ONDITIONS .......................................................................... ATA/ ATAPI ................................................. 17 - USB 2 ...

Page 5

... EVICE F 6. IGURE OST TERMINATING IGURE EVICE F 7.1 - GL811E 48 P IGURE F 7.3 - GL811E 64 P IGURE ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller LIST OF FIGURES D .................................................................9 INOUT IAGRAM D ...............................................................10 INOUT IAGRAM ......................................................................................13 M DMA D ULTIWORD ATA M DMA D ULTIWORD ...

Page 6

... D ABLE OR PAD TYPE ABLE WITCHING T 6 DMA ABLE LTRA T 8 ABLE RDERING ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller LIST OF TABLES ......................................................................................11 ...................................................................................15 ATINGS C .......................................................................15 ONDITIONS (F OR PAD TYPE (F OR PAD TYPE =3.6V) ............................................16 MIA CC C ...

Page 7

... GL811E can support various kinds of ATA / ATAPI device. There are totally 4 endpoints in the GL811E controller, Control (0), Bulk In (1), Bulk Out (2), and Interrupt (3). By complies with the USB Storage Class specification ver.1.0 (Bulk only protocol), the GL811E can support not only plug and play but also Windows XP/ 2000/ ME default driver ...

Page 8

... Provides LED indicator for Full Speed and High Speed (only for 64 pin package). 12 MHz external clock to provide better EMI. 3.3V power input; 5V tolerance pad for IDE interface. Supports Wakeup ability. Available in 48-pin LQFP and 64-pin LQFP package. ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Page 8 ...

Page 9

... CHAPTER 3 PIN ASSIGNMENT 3.1 Pinouts Figure 3 Pin LQFP Pinout Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Page 9 ...

Page 10

... DVCC1 56 IODD4 57 IODD5 58 IODD6 59 IODD7 60 GPIO1 61 PWR_CT 62 L F_LED 63 H_LED 64 Figure 3 Pin LQFP Pinout Diagram ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller GL811E LQFP - AVCC1 30 RREF AGND0 29 28 DMH 27 DMF 26 DPH 25 DPF 24 AVCC0 23 RPU ...

Page 11

... RREF TEST 29 CS0_ 30,31 DA0~1 - DA2 INTRQ 32 33 DMACK_ 34 IORDY ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Table 3.1 - Pin Descriptions B 1 GPIO7 (**) (tri) 3 programmable B 5~8 IDE data bus 8~11 (*****) (tri) 56,9 P Digital VCC 55,10 P Digital ground B 11~14 IDE data bus 12~15 (*****) ...

Page 12

... Automatic output low when suspend pu Internal pull up pd Internal pull down odpu Open drain with internal pull up tri Tri-state ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller O 47 IDE read signal (*****) (tri IDE write signal (*****) (tri) I ...

Page 13

... IODD15-0 IDE INTRQ 4 CBLID_ Engine DMARQ IORDY 12-96MHz X10 Clkgen 12MHz X40 ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller CPU CONTROL FIFO TXFIFO0 SIE TXFIFO1 RXFIFO0 RXFIFO1 Figure 4.1 - Block Diagram Control Register RPU CLK30 DPF RXSTS ...

Page 14

... MDMA mode, 96MHz for UDMA mode, and 30MHz clock for UTMI, SIE, and FIFO. 6. CPU The CPU is the control center of GL811E. It’s an 8-bit micro controller operating in 15MHz, 7.5 MIPS. After receiving a USB command, it decodes the host command, then it re-assigns tasks to the IDE engine, GPIO, FIFO, and response proper data/status to USB host ...

Page 15

... Leakage current for pads with internal pull up or pull down resistor Pad internal pull down resister Pad internal pull up resister Supply current ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Table 6.1 - Maximum Ratings Parameter Table 6.2 - Temperature Conditions Min. Max. ...

Page 16

... Hi-Z state data line leakage Driver output resistance 6.3.4 Switching Characteristics Parameter X1 crystal frequency X1 cycle time D+/D- rise time with 50pF loading D+/D- fall time with 50pF loading ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller =3.6V 1. 15K to GND ) L Table 6 ...

Page 17

... AC Characteristics- ATA/ ATAPI The GL811E complies with ATA / ATAPI-6 specification rev 1.0, which supports following data transfer modes: 1. DMA (Direct Memory Access) data transfer: DMA data transfer means of data transfer between device and host memory without host processor intervention. - Multiword DMA: Multiword DMA is a data transfer protocol used with the READ DMA, WRITE DMA, READ DMA QUEUED, WRITE DMA QUEUED and PACKET commands ...

Page 18

... IORDY DMACK_ shall remain negated during a register transfer. ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller from the assertion of DIOR_ or DIOW_ but causes IORDY to be asserted before IORDY is released prior to negation and may be asserted for no A ...

Page 19

... KW t DIOR_ to DMARQ delay LR t DIOW_ to DMARQ delay LW t CS(1:0) (max) valid to DIOR_/ DIOW_ M t CS(1:0) hold N t DMACK_ to read data released Z ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller ) A Timing (ns) 2000 1000 300 900 900 - - - Timing (ns) ...

Page 20

... The host shall not assert DMACK_ or negate both CS0_ and CS1_ until the assertion of DMARQ is detected. The maximum time from the assertion of DMARQ to the assertion of DMACK_ or the negation of both CS0_ and CS1_ is not defined. Figure 6.1 - Initiating a Multiword DMA Data Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Page 20 ...

Page 21

... DIOR_ or DIOW_ pulse. If all data for the command has not been transferred, the device shall reassert DMARQ again at any later time to resume the DMA operation. Figure 6.3 - Device Terminating a Multiword DMA Data Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller of the assertion of the current L Page 21 ...

Page 22

... If the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACK_ or may negate DMARQ at any time after detecting that DMACK_ has been negated. Figure 6.4 - Host terminating a Multiword DMA Data Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Page 22 ...

Page 23

... RFS t 160 125 IORDYZ ZIORDY ACK ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Mode 2 Mode 3 (in ns) (in ns) max min max min max 120 115 200 ...

Page 24

... Figure 6.6 - Sustained Ultra DMA Data-In Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Page 24 ...

Page 25

... Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.8 - Device Terminating an Ultra DMA Data-In Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller after RP Page 25 ...

Page 26

... Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.9 - Host Terminating an Ultra DMA Data-In Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Page 26 ...

Page 27

... Figure 6.11 - Sustained Ultra DMA Data-Out Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Page 27 ...

Page 28

... DDMARDY_ is negated the t timing is not satisfied, the device may receive zero, one, or two more data words from the host. SR Figure 6.12 - Device Pausing an Ultra DMA Data-Out Burst ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller after RP Page 28 ...

Page 29

... Notes: The definitions for the DIOW_:STOP, DIOR_:HDMARDY_:HSTROBE and IORDY:DDMARDY_:DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. Figure 6.13 - Host terminating an Ultra DMA data-out burst ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Page 29 ...

Page 30

... Figure 6.14 - Device Terminating an Ultra DMA Data-Out Burst 6.5 AC Characteristics - USB 2.0 The GL811E conforms to all timing diagrams and specifications for Universal Serial Bus specification rev. 2.0. Please refer to this specification for more information. ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller ...

Page 31

... SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. Figure 7.1 - GL811E 48 Pin LQFP Package ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller D D1 ...

Page 32

... SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. Figure 7.3 - GL811E 64 Pin LQFP Package ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller D D1 ...

Page 33

... GL811E -MSNXX 64-pin LQFP GL811E -MNNXX 48-pin LQFP GL811E -MSGXX 64-pin LQFP GL811E -MNGXX 48-pin LQFP ©2000-2006 Genesys Logic Inc. - All rights reserved. GL811E USB 2.0 to ATA/ATAPI Bridge Controller Table 8.1 - Ordering Information Package Normal/Green Normal Package Normal Package Green Package Green Package Version ...

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