AK4352VT AKM Semiconductor, Inc., AK4352VT Datasheet
AK4352VT
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AK4352VT Summary of contents
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ASAHI KASEI The AK4352 is an 18bit low voltage & power stereo DAC for digital audio system. The AK4352 uses the new developed Multi-Bit architecture, this new architecture achieves DR=94dB at low voltage operation. The AK4352 includes post filter with ...
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... ASAHI KASEI n Ordering Guide AK4352VT AKD4352 n Pin Layout MCLK BICK 3 SDATA 4 LRCK 5 DIF0 6 DIF1 7 DEM 8 No. Pin Name I/O 1 MCLK BICK I 4 SDATA I 5 LRCK I 6 DIF0 I 7 DIF1 I 8 DEM I 9 VSS - 10 VDD - 11 VREF I 12 VCMR O 13 AOUTR ...
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ASAHI KASEI (VSS=0V;Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Input Voltage Ambient Operating Temperature Storage Temperature Note 1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may results in permanent damage ...
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ASAHI KASEI (Ta=25 C; VDD=2.0V, VREF=VDD; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 18bit Input Data; Measurement frequency=10Hz 20kHz; R Parameter Dynamic Characteristics THD+N (0dB Output) Dynamic Range (-60dB Output, A-weight) S/N (A-weight) Interchannel Isolation DC Accuracy Interchannel Gain Mismatch Gain Drift Output ...
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ASAHI KASEI (Ta=25 C; VDD=1.8 3.6V; fs=44.1kHz; DEM= “L”) Parameter Digital filter Passband -0.1dB (Note 6) -6.0dB Stopband (Note 6) Passband Ripple Stopband Attenuation Group Delay (Note 7) Digital Filter + Analog Filter Frequency Response 0 20.0kHz Note 6. The ...
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ASAHI KASEI (Ta=25 C; VDD=1.8 3.6V) Parameter 256fs: Master Clock Timing Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High LRCK Frequency (Note 8) Serial Interface Timing BICK Period BICK Pulse Width Low Pulse Width High ...
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ASAHI KASEI n System Clock The external clocks which are required to operate the AK4352 are MCLK (256fs/384fs) LRCK (fs), BICK (32fs ). The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The frequency ...
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ASAHI KASEI n Audio Serial Interface Format The AK4352 interfaces with external system by using SDATA, BICK and LRCK pins. Four types of data format are available and one of them is selected by setting DIF0 and DIF1. Format 0 ...
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ASAHI KASEI Lch LRCK BICK SDATA 16bit SDATA 18bit n De-emphasis filter The AK4352 includes the digital de-emphasis filter (tc=50/ IIR filter. This filter corresponds to 44.1kHz sampling. The de-emphasis is enabled ...
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ASAHI KASEI n System Reset The AK4352 should be reset once by bringing PD = “L” upon power-up. The internal timing starts clocking by LRCK “ ” upon exiting reset. Figure 6 shows the system connection diagram. An evaluation board ...
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ASAHI KASEI 1. Grounding and Power Supply Decoupling Figure 6 shows the power supply connection example. VDD is supplied from analog supply in system. Decoupling capacitors for high frequency should be as near to the AK4352 device as possible, with ...
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ASAHI KASEI 16pin TSSOP (Unit: mm) *5 0.22 0.1 Seating Plane NOTE: Dimension "*" does not include mold flash. n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: M0040-E-02 PACKAGE 9 ...
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ASAHI KASEI These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability ...