AK4351VT AKM Semiconductor, Inc., AK4351VT Datasheet
AK4351VT
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AK4351VT Summary of contents
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ASAHI KASEI The AK4351 is a high cost performance 18bit stereo DAC for low-end digital audio systems. The modulator in the AK4351 uses the new developed Advanced Multi Bit architecture with wide dynamic range. The analog outputs are filtered in ...
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... ASAHI KASEI n Ordering Guide AK4351VT AKD4351 n Pin Layout DIF1 1 LRCK 2 BICK 3 SDATA MCLK 6 DEM 7 CKS 8 No. Pin Name I/O 1 DIF1 I 2 LRCK I 3 BICK I 4 SDATA MCLK I 7 DEM I 8 CKS I 9 TST O 10 AOUTR O 11 AOUTL O 12 VCOM ...
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ASAHI KASEI (VSS=0V; Note 1) Parameter Power Supply Input Current, Any Pin Except Supplies Input Voltage Ambient Operating Temperature Storage Temperature Note:1. All voltages with respect to ground. WARNING: Operation at or beyond these limits may result in permanent damage ...
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ASAHI KASEI (Ta=25°C; VDD=5.0V; fs=44.1kHz; BICK=64fs; Signal Frequency=1kHz; 18bit Input Data; Measurement frequency=10Hz ~ 20kHz; R Parameter Resolution Dynamic Characteristics THD+N (0dB Output) Dynamic Range (-60dB Output, A-weight) S/N (A-weight) Interchannel Isolation (1kHz) Interchannel Gain Mismatch DC Accuracy Gain Drift ...
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ASAHI KASEI (Ta=25°C; VDD=4.5 ~ 5.5V; fs=44.1kHz; DEM=”L”) Parameter Digital filter ±0.05dB (Note 7) Passband -6.0dB Stopband (Note 7) Passband Ripple Stopband Attenuation Group Delay (Note 8) Digital Filter + LPF Frequency Response 0 ~ 20.0kHz Note: 7. The passband ...
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ASAHI KASEI (Ta=25°C; VDD=4.5 ~ 5.5V Parameter Master Clock Timing 256fs: Pulse Width Low Pulse Width High 384fs: Pulse Width Low Pulse Width High LRCK Frequency Duty Cycle Serial Interface Timing BICK Period BICK Pulse Width Low Pulse ...
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ASAHI KASEI n Timing Diagram MCLK LRCK BICK LRCK tBLR BICK SDATA PD M0022-E-04 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Clock Timing tLRB tSDS tSDH Serial Interface Timing tPD Power-down - 7 - [AK4351] VIH VIL VIH VIL VIH ...
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ASAHI KASEI n System Clock The external clocks, which are required to operate the AK4351, are MCLK, LRCK and BICK. The master clock (MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to ...
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ASAHI KASEI Lch LRCK ...
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ASAHI KASEI n Power-down The AK4351 is placed in the power-down mode by bringing PD pin “L” and the anlog outputs are floating(Hi-Z). Figure 4 shows an example of the system timing at the power-down and power-up. PD Internal Normal ...
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ASAHI KASEI Figure 5 shows the system connection diagram. An evaluation board [AKD4351] is available in order to allow an easy study on the layout of a surrounding circuit Decoder 3 4 Reset 5 External 6 Clock 7 ...
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ASAHI KASEI 1. Grounding and Power Supply Decoupling VDD and VSS are supplied from analog supply and should be separated from system digital supply. Decoupling capacitor, especially 0.1mF ceramic capacitor for high frequency should be placed as near to VDD ...
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ASAHI KASEI 16pin TSSOP (Unit: mm) *5 ± 0.22 0.1 Seating Plane NOTE: Dimension "*" does not include mold flash. n Package & Lead frame material Package molding compound: Lead frame material: Lead frame surface treatment: M0022-E-04 PACKAGE ...
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ASAHI KASEI · These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. · AKM assumes ...