HFA1135IBZ96 Intersil, HFA1135IBZ96 Datasheet - Page 6

• Manufacturer Part Number: HFA1135IBZ96
• Description: IC OPAMP CFA 360MHZ LP 8-SOIC
• Manufacturer: Intersil

Specifications of HFA1135IBZ96

• Applications: Current Feedback
• Number Of Circuits: 1
• -3db Bandwidth: 360MHz
• Slew Rate: 1530 V/µs
• Current - Supply: 6.9mA
• Current - Output / Channel: 60mA
• Voltage - Supply, Single/dual (±): ±4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Evaluation Board
The performance of the HFA1135 may be evaluated using
the HFA11XX evaluation board (part number
HFA11XXEVAL). Please contact your local sales office for
information. When evaluating this amplifier at a gain of +2,
the two 510Ω gain setting resistors on the evaluation board
should be changed to 250Ω.
The layout and schematic of the board are shown in Figure 2.
NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics part number
08-350000-10.
Limiting Operation
General
The HFA1135 features user programmable output clamps to
limit output voltage excursions. Limiting action is obtained by
applying voltages to the V
10µF
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
IN
0.1µF
510Ω
50Ω
-5V
+IN
1
2
3
4
BOARD SCHEMATIC
BOTTOM LAYOUT
TOP LAYOUT
510Ω
H
1
and V
6
V
H
L
V
GND
8
7
6
5
L
terminals (pins 8 and 5)
OUT
V-
GND
50Ω
0.1µF
V+
V
H
GND
OUT
V
L
10µF
+5V
HFA1135
of the amplifier. V
the lower limit level. If the amplifier tries to drive the output
above V
voltage at V
low input bias currents of the limit pins allow them to be
driven by simple resistive divider circuits, or active elements
such as amplifiers or DACs.
Limit Circuitry
Figure 3 shows a simplified schematic of the HFA1135 input
stage, and the high limit (V
feedback amplifiers, there is a unity gain buffer (Q
between the positive and negative inputs. This buffer forces
-IN to track +IN, and sets up a slewing current of:
I
This current is mirrored onto the high impedance node (Z) by
Q
output via another unity gain buffer. If no limiting is utilized,
the high impedance node may swing within the limits defined
by Q
quiescent value, the current flowing through -IN is reduced to
only that small current (-I
the final voltage.
Tracing the path from V
voltage on the high impedance node. V
(Q
begins to conduct whenever the high impedance node
reaches a voltage equal to Q
and Q
R
limit inputs floating. A similar description applies to the
symmetrical low limit circuitry controlled by V
+IN
SLEW
1
X3
N6
provides a pull-up network to ensure functionality with the
-Q
FIGURE 3. HFA1135 SIMPLIFIED V
P4
and Q
N5
X4
= (V
and Q
H
). Thus, Q
, where it is converted to a voltage and fed to the
, or below V
-IN
Q
Q
V-
V+
P6
H
N1
P1
or V
Q
N4
Q
) to set up the base voltage on Q
- V
N3
P3
. Note that when the output reaches its
OUT
V-
H
L
P5
Q
Q
I
sets the upper output limit, while V
LIMIT
(± the limit accuracy), respectively. The
N2
P2
)/R
L
limits node Z whenever Z reaches V
V+
, the clamp circuitry limits the output
H
F
V
BIAS
-IN
to Z illustrates the effect of the limit
-IN
+ V
H
) circuitry. As with all current
Q
Q
P5
) required to keep the output at
-IN
N4
P4
Z
’s base voltage + 2V
Q
/R
Q
N5
P5
G
H
(EXTERNAL)
H
+1
LIMIT CIRCUITRY
decreases by 2V
Q
Q
R
N6
P6
F
L
.
P5
200Ω
X1
. Q
R
BE
1
P5
- Q
L
V
(Q
sets
V
X2
50kΩ
H
OUT
BE
P5
H
)
.