PPC403GA-JC25C1 IBM Microelectronics, PPC403GA-JC25C1 Datasheet

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PPC403GA-JC25C1

Manufacturer Part Number
PPC403GA-JC25C1
Description
32-Bit RISC Embedded Controller
Manufacturer
IBM Microelectronics
Datasheet

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PowerPC 403GA
32-Bit RISC
Embedded Controller
Features
Applications
Specifications
PowerPC
architecture
Glueless interfaces to DRAM, SRAM,
ROM, and peripherals, including byte and
half-word devices
Separate instruction cache and write-back
data cache, both two-way set-associative
Minimized interrupt latency
Individually programmable on-chip
controllers for:
–Four DMA channels
–DRAM, SRAM, and ROM banks
–Peripherals
–Serial port
–External interrupts
Flexible interface to external bus masters
Hardware multiplier and divider for faster
integer arithmetic
Thirty-two 32-bit general purpose registers
Set-top boxes
Consumer electronics and video games
Telecommunications and networking
Office automation (printers, copiers, fax
machines)
Personal digital assistants (PDA)
25MHz, and 33MHz, and 40MHz versions
Interfaces to both 3V and 5V technologies
Low-power 3.3V operation with built-in
power management and stand-by mode
Low-cost 160 lead PQFP package
0.5 m triple-level-metal CMOS
RISC CPU and instruction set
Overview
The PowerPC 403GA 32-bit RISC embedded
controller offers high performance and functional
integration with low power consumption. The
403GA RISC CPU executes at sustained speeds
approaching one cycle per instruction. On-chip
caches and integrated DRAM and SRAM control
functions reduce chip count and design
complexity in systems, while improving system
throughput.
External I/O devices or SRAM/DRAM memory
banks can be directly attached to the 403GA bus
interface unit (BIU). Interfaces for up to eight
memory banks and I/O devices, including a
maximum of four DRAM banks, can be
configured individually, allowing the BIU to
manage devices or memory banks with differing
control, timing, or bus width requirements.
(Address
Control)
Data
Bus
and
4-Channel
Controller
Controller
Interrupt
JTAG
Data
Sheet
Port
Port
Serial
DMA
Bus
Address
Bus Interface Unit
DRAM Controller
Controls
DRAM
On-chip
Bus
Peripheral
Instruction
Cache Unit
RISC Execution Unit
Timers
SRAM, ROM, I/O
I/O Controller
Cache Unit
Controls
Data

Related parts for PPC403GA-JC25C1

PPC403GA-JC25C1 Summary of contents

Page 1

PowerPC 403GA 32-Bit RISC Embedded Controller Features • PowerPC RISC CPU and instruction set architecture • Glueless interfaces to DRAM, SRAM, ROM, and peripherals, including byte and half-word devices • Separate instruction cache and write-back data cache, both two-way set-associative ...

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IBM PowerPC 403GA The 403GA RISC controller consists of a pipe- lined RISC processor core and several peripheral interface units: BIU, DMA controller, asynchro- nous interrupt controller, serial port, and JTAG debug port. The RISC processor core includes the internal ...

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Memory Addressing Regions The 403GA can address an effective range of four gigabytes, mapped to 3.5GB (256MB for SRAM/ROM or other I/O, 256MB ...

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IBM PowerPC 403GA The data cache may be disabled for a 128MB memory region via control bits in the data cache control register per-page basis if the MMU is enabled for data translation. A separate bypass path ...

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SRR0 and SRR1 to be loaded into the program counter and the MSR, respectively. Execution then begins at the address in the program counter. The four critical exceptions ...

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... This mode does not alter the performance of the processor. P/N Code Table 3. PPC403GA Part Number MHz Part Number 25 PPC403GA-JC25C1 33 PPC403GA-JC33C1 40 PPC403GA-JC40C1 Notes: 1. The dash number indicates the speed version. 2. The characters in the dash number indicate package type (J), revision level (C), and commercial version (C) ...

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... INT4 READY BUSERROR ERROR RESET BOOTW TESTC/ [HOLDPRI] TS0 TS1 TS2 TS3 TS4 TS5 32 TS6 A6 • • • A29 PPC403GA RISC Controller Serial DMA Port Controls External SRAM Master Controls Interrupts SRAM/DRAM Controls DRAM Controls Trace JTAG Status Data Address Bus ...

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IBM PowerPC 403GA Pin Functional Descriptions Active-low signals are shown with overbars: DMAR0. Multiplexed signals are alphabetized under the first (unmultiplexed) signal names on the same pins. The logic symbol on the preceding page shows all 403GA signals arranged by ...

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I/O Signal Name Pin Type A29 119 I/O AMuxCAS 139 O BootW 11 I BusError 12 I BusReq/ 135 O DMADXFER CAS0 142 O CAS1 143 O CAS2 144 O CAS3 145 O CINT 36 I CS0 155 O CS1 ...

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IBM PowerPC 403GA I/O Signal Name Pin Type CS2 153 O CS3 152 O CS4/RAS3 151 O CS5/RAS2 148 O CS6/RAS1 147 O CS7/RAS0 146 ...

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I/O Signal Name Pin Type D22 71 I/O D23 72 I/O D24 73 I/O D25 74 I/O D26 75 I/O D27 76 I/O D28 77 I/O D29 78 I/O D30 79 I/O D31 82 I/O DMAA0 156 O DMAA1 157 ...

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IBM PowerPC 403GA I/O Signal Name Pin Type DSR/CTS 28 I DTR/RTS 88 O EOT0/TC0 128 I/O EOT1/TC1 131 I/O EOT2/TC2 132 I/O EOT3/TC3/ 133 I/O XSize0 Error 136 O 12 Table 4. 403GA Signal Descriptions Function Data Set Ready ...

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I/O Signal Name Pin Type GND 101 102 111 121 130 141 150 Halt 9 I HoldAck 134 O HoldReq 14 I INT0 31 I INT1 32 I ...

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IBM PowerPC 403GA I/O Signal Name Pin Type IVR 39 OE/XSize1 126 O/I Ready 13 I RecvD 27 I Reset 91 I/O R/W 127 I/O SerClk 26 I SysClk 22 I TCK 6 I TDI 8 I TDO 16 O ...

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I/O Signal Name Pin Type TestB 24 I TestC/Hold Pri TestD 38 I TimerClk 25 I TMS 7 I TS0 17 O TS1 18 O TS2 19 O TS3 86 O/I TS4 85 O/I TS5 84 O/I TS6 ...

Page 16

IBM PowerPC 403GA I/O Signal Name Pin Type 100 120 129 140 149 160 XmitD Table 4. 403GA Signal Descriptions Function Power. All power pins must be ...

Page 17

Table 5. Signals Ordered by Pin Number Pin Signal Name Pin Signal Name Pin Signal Name Pin 1 GND 33 INT2 2 DMAR0 34 INT3 3 DMAR1 35 INT4 4 DMAR2 36 CINT 5 DMAR3/XREQ 37 TestC/HoldPri ...

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IBM PowerPC 403GA PQFP Mechanical Drawing (Top View) 120 121 31.2 0.25 1.228 0.01 28 0.2 1.102 0.008 160 1 0.25 Min 0.01 0.65 Basic 0.0256 0.012 Notes: 1. Packages with date codes later than the 26th week of 1998 ...

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Package Thermal Specifications The 403GA is designed to operate within the case temperature range from -40°C to 120°C. Thermal resistance values are shown in Table 6: Table 6. Thermal Resistance (°C/Watt) Airflow-ft/min (m/sec) Parameter 0 (0) Junction to case 2 ...

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IBM PowerPC 403GA DC Specifications Symbol V Input low voltage (except for SysClk Input low voltage for SysClk ILC V Input high voltage (except for SysClk Input high voltage for SysClk IHC V Output low voltage ...

Page 21

SysClk Timing Waveform Symbol Parameter F SysClk clock input frequency C T SysClk clock period Clock edge stability CS T Clock input high time CH T Clock input low time CL T Clock ...

Page 22

IBM PowerPC 403GA Table 13. 403GA Serial Port Output Timings Symbol Parameter T T Output hold, output valid time , DTR/RTS OH1 , OV1 T T XmitD , OH2 OV2 1. Output times are measured with ...

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Table 14. 403GA Synchronous Input Timings Symbol Parameter T Input setup IS1 T IS2 T D0:31 (to SysClk) IS3 T D0:31 (to CAS) ISCAS T IS4 T IS5 T IS6 T IS7 T IS8 T IS9 T Input ...

Page 24

IBM PowerPC 403GA Table 15. 403GA Asynchronous Input Timings Symbol Parameter T Input setup time IS T CINT IS10 T DMAR0:3 IS11 T EOT0:3 IS12 T HALT IS13 T INT0:4 IS14 T Reset IS15 T Input hold time IH T ...

Page 25

Table 16. 403GA Synchronous Output Timings Symbol Parameter Output hold, output valid time A6:31 , OH1 OV1 T T AMuxCAS , OH2 OV2 T T BusReq , OH3 OV3 T T CAS0:3 , ...

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IBM PowerPC 403GA Output Derating for Capacitance and Voltage Derating Equations for Output Delays ...

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Output Rise and Fall Time Derating Derating Equations for Output Rise and Fall Times 2ns + 2.5ns + Output Voltage ...

Page 28

IBM PowerPC 403GA Receiver Input Voltage vs DC Input Current 100 Note: 1. Applies to receivers for asynchronous inputs on pins 2-9, 11,13, 23, 25-28, 31-38, and 91, and synchronous inputs on pins 5, ...

Page 29

IBM PowerPC 403GA Reset and HoldAck The following table summarizes the states of signals on output pins when Reset or HoldAck is active. Table 17. Signal States During Reset or Hold Acknowledge Signal Names State When Reset Active A6:29 Floating ...

Page 30

Transfer Size Byte 8-Bit Bus Byte Width Byte Byte Transfer Size Half-word Half-word 16-Bit Bus Byte Width Byte Byte Byte Transfer Size Word Half-word Half-word 32-Bit Bus Width Byte Byte Byte Byte Address Bus Multiplexing To support memories and I/O ...

Page 31

IBM PowerPC 403GA SRAM Read-Write-Read with Zero Wait and One Hold 1 SysClk 1 A6:29, WBE2[A30], WBE3[A31] R/W CSx OE 2 WBE0:3 D0:31 BusError Bank Register Bit Settings Burst Bus SLF Mode Width Bit 13 Bit 14 Bits 15:16 0 ...

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SRAM, ROM, or I/O Write Request with Wait and Hold 1 SysClk 1 A6:29, WBE2[A30], WBE3[A31] R/W 3 CSx 3 OE 2,3 WBE0:3 D0:31 BusError Bank Register Bit Settings Burst Bus SLF Mode Width Bit 13 Bit 14 Bits 15:16 ...

Page 33

IBM PowerPC 403GA SRAM, ROM, or I/O Read Request, Wait Extended with Ready 1 SysClk 1 A6:29, WBE2[A30], WBE3[A31] R/W 3 CSx 3 OE 2,3 WBE0:3 D0:31 5 Ready BusError Bank Register Bit Settings Burst Bus SLF Mode Width Bit ...

Page 34

SRAM, ROM or I/O Burst Read with Wait and Hold 1 SysClk 1 A6:29, WBE2[A30], WBE3[A31] R/W 3 CSx BLast 2,3 WBE0:3 3 BE0:3 D0:31 BusError Bank Register Bit Settings Burst Bus Ready SLF Mode Width Enable ...

Page 35

IBM PowerPC 403GA SRAM, ROM or I/O Burst Write with Wait, Burst Wait, and Hold SysClk 1 A6:29, WBE2[A30], WBE3[A31] R/W 3 CSx BLast 2,3 WBE0:3 3 BE0:3 D0:31 BusError Bank Register Bit Settings Burst Bus Ready ...

Page 36

DRAM 2-1-1-1 Page Mode Read 1 SysClk RAS A11:29, WBE2[A30], Row WBE3[A31] AMuxCAS R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 BusError Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit 14 Bits Bit 17 15:16 0 ...

Page 37

IBM PowerPC 403GA DRAM 3-2-2-2 Page Mode Write 1 SysClk RAS CAS A11:29 Row AMuxCAS R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 BusError Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit 14 Bits Bit 17 ...

Page 38

DRAM Read-Write-Read, One Wait 1 2 SysClk RAS CAS A11:29 Row1 AMuxCAS R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 BusError Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit 14 Bits Bit 17 15: ...

Page 39

IBM PowerPC 403GA DMA Buffered Single Transfer from Peripheral to 3-Cycle DRAM 1 2 SysClk Sync DMAR DMAA A11:29 R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 OE WBE0:3 Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 ...

Page 40

DMA Fly-By Single Transfer, Write to 3-Cycle DRAM 1 2 SysClk Sync Sync DMAR DMAA DMADXFER A11:29 R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit 14 Bits Bit ...

Page 41

IBM PowerPC 403GA DMA Fly-By Continuous Burst to 3-Cycle DRAM 1 SysClk Sync DMAR DMAA DMADXFER A11:29 R/W RAS CAS0:3 DRAMOE DRAMWE D0:31 Bank Register Bit Settings Bus Ext RAS-to- SLF ERM Width Mux Bit 13 Bit 14 Bits Bit ...

Page 42

External Master Nonburst DRAM Read with HoldReq/HoldAck 1 2 SysClk Ext Bus Master HoldReq HoldAck 1 XReq R/W 1 XSize0:1 1 XAck 2 A4:31 403 Master D0:31 403 Master DRAM Control AMuxCAS RASx CAS0:3 DRAMOE DRAMWE Bank Register Bit Settings ...

Page 43

IBM PowerPC 403GA External Master DRAM Burst Write, 3-2-2-2 Page Mode SysClk Ext Bus Master XReq BSel HoldReq HoldAck 1,3 XReq R/W 1,2,3 XSize0:1 1 XAck 4 A4:31 D0:31 DRAM Control AMuxCAS RASx CAS0:3 DRAMOE DRAMWE Bank ...

Page 44

... Copyright IBM Corporation 1996,1998. All rights reserved. Printed in the USA on recycled paper. 12-98 IBM Microelectronics, PowerPC, PowerPC Architecture, and 403GA are trademarks, IBM and the IBM logo are registered trademarks of IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility of liability for any use of the information contained herein ...

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