IBM25PPC750FL-GR0133T IBM MICROELECTRONICS, IBM25PPC750FL-GR0133T Datasheet

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IBM25PPC750FL-GR0133T

Manufacturer Part Number
IBM25PPC750FL-GR0133T
Description
MPU 750xx RISC 32-Bit 0.13um 600MHz 1.8V/2.5V/3.3V 750-Pin CBGA Tray
Manufacturer
IBM MICROELECTRONICS
Datasheet

Specifications of IBM25PPC750FL-GR0133T

Package
750CBGA
Device Core
PowerPC
Family Name
750xx
Number Of Cpu Cores
1
Data Bus Width
32 Bit
Maximum Speed
600 MHz
I/o Voltage
1.8|2.5|3.3 V
Operating Temperature
-40 to 105 °C
Title Page
PowerPC 750FL RISC Microprocessor
Datasheet
DD2.X
Version 6.0
Preliminary
April 27, 2007

IBM25PPC750FL-GR0133T Summary of contents

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PowerPC 750FL RISC Microprocessor Datasheet DD2.X Version 6.0 Preliminary April 27, 2007 Title Page ...

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Copyright and Disclaimer Copyright International Business Machines Corporation 2007 © All Rights Reserved Printed in the United States of America April 2007 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or ...

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Preliminary Contents List of Figures ................................................................................................................. 5 List of Tables ................................................................................................................... 7 1. General Information .................................................................................................... 9 1.1 Features ............................................................................................................................................ 9 1.2 Design Level Considerations and Features .................................................................................... 12 1.3 Processor Version Register ............................................................................................................ 12 1.4 Part Number Information ................................................................................................................. ...

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PowerPC 750FL RISC Microprocessor 5.8.2 Internal Package Conduction ................................................................................................. 59 5.8.3 Minimum Heat Sink Requirements ........................................................................................ 60 5.8.4 Heat Sink Mounting ................................................................................................................ 61 5.8.5 Thermal Assist Unit ................................................................................................................ 61 5.8.6 Adhesives and Thermal Interface Materials ........................................................................... 62 5.8.7 Thermal Interface ...

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Preliminary List of Figures Figure 1-1. Part Number Legend .............................................................................................................. 13 Figure 2-1. PowerPC 750FL RISC Microprocessor Block Diagram ......................................................... 14 Figure 3-1. SYSCLK Input Timing Diagram .............................................................................................. 20 Figure 3-2. Linear Sweep Modulation Profile ........................................................................................... 21 Figure 3-3. Input ...

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PowerPC 750FL RISC Microprocessor List of Figures Page Preliminary 750flds60LOF.fm.6.0 April 27, 2007 ...

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Preliminary List of Tables Table 1-1. 750FL Microprocessor PVR ................................................................................................... 12 Table 2-1. 750FL Microprocessor General Parameters .......................................................................... 15 Table 3-1. Absolute Maximum Ratings ................................................................................................... 16 Table 3-2. Recommended Operating Conditions .................................................................................... 17 Table 3-3. Package Thermal Characteristics .......................................................................................... 17 ...

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PowerPC 750FL RISC Microprocessor List of Tables Page Preliminary 750flds60LOT.fm.6.0 April 27, 2007 ...

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Preliminary 1. General Information The IBM® PowerPC® 750FL RISC microprocessor is a 32-bit implementation of the IBM PowerPC family of reduced instruction set computer (RISC) microprocessors. This document contains pertinent physical and electrical characteristics of the IBM PowerPC 750FL. The ...

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PowerPC 750FL RISC Microprocessor – Early-out multiply – Thirty-two 32-bit general purpose registers • Floating-point unit – Support for IEEE-754 standard single- and double-precision floating-point arithmetic – Optimized for single-precision multiply and add – Thirty-two, 64-bit floating point registers – ...

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Preliminary • Power – Low power consumption with low voltage application at lower frequency – Dynamic power management – Three static power save modes (doze, nap, and sleep) – Thermal Assist Unit (TAU) • Bus interface – 32-bit address bus ...

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PowerPC 750FL RISC Microprocessor 1.2 Design Level Considerations and Features The 750FL microprocessor supports several unique features including those in the following list. The IBM application note Differences between the PowerPC 750FX, 750, 750CX, and 750CXe Microprocessors provides a more ...

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... Preliminary 1.4 Part Number Information Figure 1-1. Part Number Legend IBM25PPC750FL-GR PowerPC 750 Family Member Process Technology Design Revision Level Package Type Process Technology Design Revision Level Package Type Performance Sort Test Conditions Reliability Grade Shipping Container 750flds60.fm.6.0 April 27, 2007 PowerPC 750FL RISC Microprocessor yy x4T “ ...

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PowerPC 750FL RISC Microprocessor 2. Overview The PowerPC 750FL RISC Microprocessor, also called the 750FL microprocessor, is targeted for high perfor- mance, low power systems using a 60x bus. The 750FL microprocessor also includes an internal 512 KB L2 cache ...

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Preliminary 2.2 General Parameters Table 2-1 provides a summary of the general parameters of the 750FL microprocessor. Table 2-1. 750FL Microprocessor General Parameters Item 0.13 μm CSOI technology, six-layer metallization plus one level of local interconnect Technology Die Size 34.3 ...

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PowerPC 750FL RISC Microprocessor 3. Electrical and Thermal Characteristics This section provides ac and dc electrical specifications and thermal characteristics for the 750FL micropro- cessor. 3.1 dc Electrical Characteristics The tables in this section describe the dc electrical characteristics for ...

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Preliminary Note: All electrical specifications (ac, dc, timing) are guaranteed only when the device is operated within the recommended operating conditions (see Table 3-2). Operation at other application conditions can also be possible; contact IBM PowerPC Application engineering for details. ...

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PowerPC 750FL RISC Microprocessor Table 3-4. dc Electrical Specifications Characteristic Input high voltage (all inputs except SYSCLK) Input low voltage (all inputs except SYSCLK) SYSCLK input high voltage SYSCLK input low voltage = applies to all OV Input leakage current, ...

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Preliminary Table 3-5. Power Consumption (Low Power) Mode Full-On Mode Maximum Typical Nap Mode Maximum Sleep Mode Typical Notes: 1. These values apply for all valid 60x buses. The values do not include I/O supply power (OV power is system ...

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PowerPC 750FL RISC Microprocessor 3.2 Clock ac Specifications Table 3-7 provides the clock ac timing specifications as defined in Figure 3-1. Table 3-7. Clock ac Timing Specifications Number (Timing Reference) Processor frequency SYSCLK frequency 1 SYSCLK cycle time 2, 3 ...

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Preliminary 3.3 Spread Spectrum Clock Generator When designing with the spread spectrum clock generator (SSCG), there are a number of design issues that must be taken into account. SSCG creates a controlled amount of long-term jitter. In order for a ...

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PowerPC 750FL RISC Microprocessor 3.4 60x Bus Input ac Specifications Table 3-8. 60x Bus Input Timing Specifications Number Characteristic 10a All inputs valid to SYSCLK (input setup) INT_, SMI_, MCP, TBEN, DRTRY, and 10b TLBISYNC (input setup) Mode select input ...

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Preliminary Figure 3-4 provides the mode select input timing diagram for the 750FL microprocessor. Figure 3-4. Mode Select Input Timing Diagram HRESET 10c MODE PINS 750flds60.fm.6.0 April 27, 2007 PowerPC 750FL RISC Microprocessor V IH 10c 11c 11c = 1.20 ...

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PowerPC 750FL RISC Microprocessor 3.5 60x Bus Output ac Specifications Table 3-9 provides the 60x bus output ac timing specifications for the 750FL microprocessor as defined and defined in Figure 3-6 Output Timing Diagram for PowerPC 750FL RISC Microprocessor on ...

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Preliminary Figure 3-5. Output Valid Timing Definition Output Driver SYSCLK Positive Output Transition Negative Output Transition The output transition is defined between SYSCLK @ VM and the respective transition level. Note: The timing definition uses an infinitely long transmission line ...

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PowerPC 750FL RISC Microprocessor Figure 3-6. Output Timing Diagram for PowerPC 750FL RISC Microprocessor VM SYSCLK SYSCLK 13 All Outputs 12 (Except TS, ARTRY ABB, DBB ARTRY Low Level Note: SYSCLK VM is defined in Section 3.2 Clock ...

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Preliminary 3.6.1 IEEE 1149.1 ac Timing Specifications The five Joint Test Action Group (JTAG) signals are test data in (TDI), test data out (TDO), test mode select (TMS), test clock (TCK), and test reset (TRST). Unless otherwise noted, JTAG specifications ...

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PowerPC 750FL RISC Microprocessor Figure 3-8. TRST Timing Diagram TRST Figure 3-9. Boundary-Scan Timing Diagram TCK Data Inputs Data Outputs Data Outputs Figure 3-10. Test Access Port Timing Diagram TCK TDI, TMS TDO TDO TDO Electrical and Thermal Characteristics Page ...

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Preliminary 4. Dimensions and Signal Assignments IBM offers a CBGA that supports 292 balls for the 750FL microprocessor package. 4.1 Module Substrate Decoupling Voltage Assignments The on-board substrate voltage-to-ground assignments for the capacitor locations are shown in Figure 4-1. Figure ...

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PowerPC 750FL RISC Microprocessor Figure 4-2. Mechanical Dimensions and Bottom Surface Nomenclature of the Reduced Lead CBGA Package A01 Corner (19X) 1 (19X) 1 292X 0.25 0.1 ...

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Preliminary 4.3 Microprocessor Ball Placement Figure 4-3. PowerPC 750FL Microprocessor Ball Placement DH31 DH25 DH26 DP2 DH22 DH19 DH18 DH16 DH15 DH14 19 A13 GND DH29 DP3 DH28 DH23 DH24 DH21 ...

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PowerPC 750FL RISC Microprocessor 4.4 Pinout Listings Table 4-1 contains the pinout listing for the 750FL microprocessor CBGA package. Table 4-1. Pinout Listing for the CBGA Package (Sheet Signal Name E20, E19, D20, C20, D19, C19, A20, ...

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Preliminary Table 4-1. Pinout Listing for the CBGA Package (Sheet Signal Name GBL W1 B2, B19, C5, C8, C13, C16, D10, D11, E3, E7, E14, E18, F10, F11, G5, G8, G13, G16, H3, H8, H9, H12, H13, ...

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PowerPC 750FL RISC Microprocessor Table 4-1. Pinout Listing for the CBGA Package (Sheet Signal Name TS B15 TSIZ[0:2] A14, B12, B11 TT[0:4] D14, B17, B14, A15, B13 C10, C11, E8, E13, F6, F9, F12, F15, J8, J9, ...

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Preliminary . Table 4-2. Signal Locations (Sheet Signal Ball Location Signal Ball Location A0 E20 DH0 W18 A1 E19 DH1 T17 A2 D20 DH2 Y20 A3 C20 DH3 Y19 A4 D19 DH4 W20 A5 C19 DH5 V19 ...

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PowerPC 750FL RISC Microprocessor Table 4-2. Signal Locations (Sheet Signal Ball Location Signal Ball Location AP0 D16 AP1 D13 AP2 A13 AP3 B8 Dimensions and Signal Assignments Page Signal Ball Location DP0 T20 TA ...

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Preliminary Table 4-3. Voltage and Ground Assignments Y15 Y16 C4 C14 D3 E10 G3 G14 P14 T10 U3 V4 V14 750flds60.fm.6.0 April 27, 2007 O V ...

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PowerPC 750FL RISC Microprocessor 5. System Design Information This section provides electrical and thermal design recommendations for the successful application of the 750FL microprocessor. For more information, see the IBM PowerPC 750L/CXe/FX/GX Microprocessor Frequently Asked Questions, the IBM PowerPC 750FX ...

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Preliminary After both PLLs are running and locked, the processor frequency can be toggled with very low latency. For example, when it is time to change back to the PLL0 frequency, there is no need to wait for PLL lock. ...

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PowerPC 750FL RISC Microprocessor 5.1.2 PLL_RNG[0:1] Definitions for Dual PLL Operation The dual PLLs on the 750FL microprocessor are configured by the PLL_CFG[0:4] and PLL_RNG[0:1] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal processor ...

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Preliminary Table 5-2. 750FL Microprocessor PLL Configuration (Sheet PLL_CFG [0:4] Binary 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Notes: 1. The 2×−2.5× processor to bus ratios are ...

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PowerPC 750FL RISC Microprocessor 5.2 PLL Power Supply Filtering The 750FL microprocessor has two separate AV clock generation phase-locked loops. Most designs are expected to use a single PLL configuration mode throughout the application. These type of designs must use ...

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Preliminary Figure 5-1. Single PLL Power Supply Filter Circuit with A1V Single PLL (A1VDD) Power Supply Filter Circuit Discrete Resistor Legend: Item Resistor C1 C2 Ferrite Bead Notes: 1. Connect to ground without a filter. ...

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PowerPC 750FL RISC Microprocessor Figure 5-2. PLL Power Supply Filter Circuit with Two AV Single PLL (A1VDD) Power Supply Filter Circuit Discrete Resistor Legend: Item Resistor C1 C2 Ferrite Bead Note: 1. Connect to ground ...

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Preliminary Figure 5-3. Dual PLL Power Supply Filter Circuits Dual PLL (AVDD) Power Supply Filter Circuits (Recommended configuration if dual PLL feature is enabled.) Discrete Resistor Discrete Resistor Item Resistor ...

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PowerPC 750FL RISC Microprocessor 5.3 Decoupling Recommendations Capacitor decoupling is required for the 750FL microprocessor. Decoupling capacitors act to reduce high frequency chip switching noise and provide localized bulk charge storage to reduce major power-surge effects. High frequency decoupling capacitors ...

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Preliminary Figure 5-4. 750FL Microprocessor Pin Locations ...

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PowerPC 750FL RISC Microprocessor Figure 5-5. Orientation and Layout of the 750FL Microprocessor Decoupling Capacitors ...

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Preliminary 5.4 Output Buffer dc Impedance The 750FL 60x drivers were characterized over various process, voltage, and temperature conditions. To measure external resistor is connected to the chip pad, either resistor is varied until ...

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PowerPC 750FL RISC Microprocessor Table 5-5 summarizes the driver impedance characteristics a designer uses to design a typical process. Table 5-5. Driver Impedance Characteristics Process 60x Impedance (Ω) Worst Typical Best Worst Typical Best Worst Typical Best 5.4.1 Input-Output Use ...

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Table 5-6. Input/Output Use (Sheet 750FL Micropro- Input/ cessor Signal Active Level Output Name A1V DD A2V DD A[0:31] High Input/Output AACK Low Input Address Termination ABB Low Input/Output AGND AP[0:3] High Input/Output ARTRY Low Input/Output Address ...

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Table 5-6. Input/Output Use (Sheet 750FL Micropro- Input/ cessor Signal Active Level Output Name DH[0:31] High Input/Output DL[0:31] High Input/Output DP[0:7] High Input/Output DRTRY Low Input GBL Low Input/Output GND HRESET Low Input INT Low Input L1_TSTCLK ...

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Table 5-6. Input/Output Use (Sheet 750FL Micropro- Input/ cessor Signal Active Level Output Name SYSCLK High Input TA Low Input TBEN High Input TBST Low Input/Output TCK High Input TDI High Input TDO High Output TEA Low ...

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Table 5-6. Input/Output Use (Sheet 750FL Micropro- Input/ cessor Signal Active Level Output Name TT[0:4] High Input/Output Low Output Notes: 1. Depends on the system design. The electrical characteristics of the 750FL microprocessor do ...

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Preliminary Figure 5-7. IBM RISCWatch JTAG to HRESET, TRST, and SRESET Signal Connector HRESET from RISCWatch System HRESET TRST from RISCWatch SRESET from RISCWatch System SRESET Note: See notes for Table 5-6 Input/Output Use on page 51. 5.5 Level Protection ...

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PowerPC 750FL RISC Microprocessor 5.6 64- or 32-Bit Data Bus Mode This mode selection varies for different design revision (DD) levels. For the 750FL DD2.X, mode setting is determined by the state of the mode signal, TLBISYNC, at the transition ...

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Preliminary 5.8.1 Heat Sink Selection Example For preliminary heat sink sizing, the die junction temperature can be expressed as follows (θ + θ + θ ) × INT SA ...

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PowerPC 750FL RISC Microprocessor Figure 5-8. Thermalloy #2328B Pin-Fin Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity For air velocity of 0.5 m/s, and an effective θ = 30°C + 5°C + ...

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Preliminary 5.8.2 Internal Package Conduction For the exposed-die packaging technology, shown in Table 3-3 Package Thermal Characteristics on page 17, the following intrinsic conduction thermal resistance paths exist: • Die junction-to-case thermal resistance (primary thermal path) • Die junction-to-lead thermal ...

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PowerPC 750FL RISC Microprocessor 5.8.3 Minimum Heat Sink Requirements The worst-case power dissipation (P tion (Low Power) on page 19. A conservative thermal management design provides sufficient cooling to maintain the junction temperature (T case ambient temperature and airflow conditions. ...

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Preliminary 5.8.4 Heat Sink Mounting Figure 5-10. Exploded Cross-Sectional View of Package with Several Heat Sink Options Heat Sink Heat Sink Clip Adhesive or Thermal Interface Material Printed Circuit Board Table 5-8. Maximum Heatsink Weight Limit for the CBGA Maximum ...

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PowerPC 750FL RISC Microprocessor 5.8.6 Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package die-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by a spring ...

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Preliminary 5.8.7 Thermal Interface and Adhesive Vendors The board designer can choose between several types of thermal interfaces. Heat sink adhesive materials must be selected based upon high conductivity and adequate mechanical strength to meet equipment shock/vibration requirements. A partial ...

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PowerPC 750FL RISC Microprocessor 5.8.8 Heat Sink Vendors The board designer can choose between several types of heat sinks to place on the 750FL microprocessor. A partial list of vendors that advertise heat sinks for Power PC devices is shown ...

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Preliminary Revision Log Date Version 6.0 April 27, 2007 • Changed the moisture sensitivity level from Section 4.2 Package on page 29. • Updated the document template. Version SA14-2768-05 June 22, 2006 • Changed Table 3-7 ...

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