IBM25PPC750FL-GR0133T IBM MICROELECTRONICS, IBM25PPC750FL-GR0133T Datasheet - Page 55

• Manufacturer Part Number: IBM25PPC750FL-GR0133T
• Description: MPU 750xx RISC 32-Bit 0.13um 600MHz 1.8V/2.5V/3.3V 750-Pin CBGA Tray
• Manufacturer: IBM MICROELECTRONICS

Specifications of IBM25PPC750FL-GR0133T

• Package: 750CBGA
• Device Core: PowerPC
• Family Name: 750xx
• Number Of Cpu Cores: 1
• Data Bus Width: 32 Bit
• Maximum Speed: 600 MHz
• I/o Voltage: 1.8|2.5|3.3 V
• Operating Temperature: -40 to 105 °C

Preliminary
Figure 5-7. IBM RISCWatch JTAG to HRESET, TRST, and SRESET Signal Connector
5.5 Level Protection
A level protection feature is included in the 750FL microprocessor. The level protection feature is available in
the 1.8 V, 2.5 V, and 3.3 V bus modes. This feature prevents ambiguous floating reference voltages by
pulling the respective signal line to the last valid or nearest valid state.
For example, if the I/O voltage level is closer to OV
closer to GND, the I/O level is pulled low. This self-latching circuitry keeps the floating inputs defined and
prevents metastability. In Table 5-6 Input/Output Use on page 51, these signals are defined as keeper in the
Level Protect column.
Keepers are not intended to force a net to a particular state. The keeper supplies a small (100 μA maximum)
amount of current, which is intended to help keep a net at the current logic state.
The level protect circuitry provides no additional leakage current to the signal I/O; however, some amount of
current must be applied to the keeper node to overcome the level protection latch. This current is process
dependent, but in no case is the current required over 100 μA.
This feature allows the system designer to limit the number of resistors in the design, optimize placement,
and reduce costs.
Note: Having a level protection (keeper) on the associated signal I/O does not replace a pull-up or pull-down
resistor that is needed by the 750FL microprocessor or a separate device located on the 60x bus. The
designer must supply any such resistors.
750flds60.fm.6.0
April 27, 2007
Note: See notes for Table 5-6 Input/Output Use on page 51.
HRESET from RISCWatch
SRESET from RISCWatch
System HRESET
TRST from RISCWatch
System SRESET
DD
, the circuit pulls the I/O level to OV
HRESET to PowerPC 750FL
TRST to PowerPC 750FL
SRESET to PowerPC 750FL
PowerPC 750FL RISC Microprocessor
System Design Information
DD.
If the I/O level is
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