IBM25PPC750FL-GR0133T IBM MICROELECTRONICS, IBM25PPC750FL-GR0133T Datasheet - Page 22

• Manufacturer Part Number: IBM25PPC750FL-GR0133T
• Description: MPU 750xx RISC 32-Bit 0.13um 600MHz 1.8V/2.5V/3.3V 750-Pin CBGA Tray
• Manufacturer: IBM MICROELECTRONICS

Specifications of IBM25PPC750FL-GR0133T

• Package: 750CBGA
• Device Core: PowerPC
• Family Name: 750xx
• Number Of Cpu Cores: 1
• Data Bus Width: 32 Bit
• Maximum Speed: 600 MHz
• I/o Voltage: 1.8|2.5|3.3 V
• Operating Temperature: -40 to 105 °C

PowerPC 750FL RISC Microprocessor
3.4 60x Bus Input ac Specifications
Table 3-8. 60x Bus Input Timing Specifications
Figure 3-3 provides the input timing diagram for the 750FL microprocessor.
Figure 3-3. Input Timing Diagram
Electrical and Thermal Characteristics
Page 22 of 65
Notes:
Number
1. Input specifications are measured from the midpoint voltage (VM) of the signal in question to the VM of the rising edge of the input
2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3-4 Mode Select Input Timing Diagram on
3. t
4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255
5. All values are guaranteed by design, and are not tested.
6. See Alternate I/O Timing for 3.3 V Bus on page 26.
7. See Table 3-2 Recommended Operating Conditions on page 17 for operating conditions.
10a
10b
10c
11a
11b
11c
VM
SYSCLK. Input and output timings are measured at the pin (see Figure 3-3).
page 23).
SYSCLK in ns to compute the actual time duration (in ns) of the parameter in question.
bus clocks after the PLL relock time during the power-on reset sequence.
ALL INPUTS
SYSCLK
SYSCLK
All inputs valid to SYSCLK (input setup)
INT_, SMI_, MCP, TBEN, DRTRY, and
TLBISYNC (input setup)
Mode select input setup to HRESET
(TLBISYNC, DRTRY)
SYSCLK to inputs invalid (input hold)
INT_, SMI_, MCP, TBEN, DRTRY, and
TLBISYNC (input hold)
HRESET to mode select input hold
(TLBISYNC, DRTRY)
Measurement Reference Voltage for
Inputs
, is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period of
10a
10b
Characteristic
VM
VMsysclk(0.65V)
VM = Midpoint Voltage (OV
VM
11a
11b
Minimum Maximum Minimum Maximum Minimum Maximum
0.65
1.0
1.5
1.5
8
0
1.8 V Mode
1, 5, 7
DD
/2)
0.65
1.5
1.5
2.5
8
0
2.5 V Mode
OV
DD
/2
0.55
1.8
1.8
2.5
8
0
3.3 V Mode
t
SYSCLK
750flds60.fm.6.0
Unit
ns
ns
ns
ns
Preliminary
April 27, 2007
2, 3, 4, 5
2, 4, 5
Notes
6