SYM53C1010-33 LSI Computer Systems, Inc., SYM53C1010-33 Datasheet
SYM53C1010-33
Specifications of SYM53C1010-33
Related parts for SYM53C1010-33
SYM53C1010-33 Summary of contents
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... Symbios PCI to Dual Channel Ultra3 SCSI Multifunction Controller Technical Manual May 2000 Version 3.0 Order Number S14025.B ® SYM53C1010-33 ® ...
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... LSI Logic officer is prohibited. Document DB14-000132-02, Third Edition (May 2000) This document describes the LSI Logic Corporation’s Symbios SYM53C1010-33 PCI to Dual Channel Ultra3 SCSI Multifunction Controller and will remain the official reference source for all revisions/releases of this product until rescinded by an update. ...
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... SCSI bus and external memory. Chapter 3, Signal descriptions. Chapter 4, and is organized by register address. Chapter 5, SCSI SCRIPTS Instruction SCRIPTS instructions that are supported by the SYM53C1010-33. Chapter 6, AC timing diagrams. Appendix A, Register Preface ® SYM53C1010-33 PCI to Dual Channel Ultra3 SCSI ...
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... Appendix B, External Memory Interface Diagram contains several example interface drawings for connecting the SYM53C1010-33 to external ROMs. Related Publications For background please contact: ANSI 11 West 42nd Street New York, NY 10036 (212) 642-4900 Ask for document number X3.131-199X (SCSI-2) Global Engineering Documents 15 Inverness Way East Englewood, CO 80112 (800) 854-7179 or (303) 397-7956 (outside U ...
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LSI Logic World Wide Web Home Page www.lsil.com LSI Logic Internet Anonymous FTP Site ftp.lsil.com (204.131.200.1) Directory: /pub/symchips/scsi PCI Special Interest Group 2575 N. E. Katherine Hillsboro, OR 97214 (800) 433-5177; (503) 693-6232 (International); FAX (503) 693-8344 Conventions Used in ...
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Preface ...
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... PCI Functional Description 2.1.1 2.1.2 2.1.3 2.1.4 2.2 SCSI Functional Description 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 Contents New Features in the SYM53C1010-33 ® Technology SCSI Performance PCI Performance Integration Ease of Use Flexibility Reliability Testability PCI Addressing PCI Bus Commands and Functions Supported Internal Arbiter PCI Cache Mode SCRIPTS Processor Internal SCRIPTS RAM ...
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... Parallel ROM Interface 2.4 Serial EEPROM Interface 2.4.1 2.4.2 2.5 Power Management 2.5.1 2.5.2 2.5.3 2.5.4 Chapter 3 Signal Descriptions 3.1 Signal Organization 3.2 Internal Pull-ups and Pull-downs on SYM53C1010 Signals 3.3 PCI Bus Interface Signals 3.3.1 3.3.2 3.3.3 3.3.4 3.3.5 3.3.6 3.3.7 3.3.8 3.4 SCSI Bus Interface Signals 3.4.1 3.4.2 viii Contents Opcode Fetch Burst Capability Load and Store Instructions JTAG Boundary Scan Testing ...
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Flash ROM and Memory Interface Signals 3.6 Test Interface Signals 3.7 Power and Ground Signals 3.8 MAD Bus Programming Chapter 4 Registers 4.1 PCI Configuration Registers 4.2 SCSI Registers 4.3 SCSI Shadow Registers Chapter 5 SCSI SCRIPTS Instruction Set ...
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... Regulated Termination for Ultra3 SCSI 2.5 Determining the Synchronous Transfer Rate 2.6 Interrupt Routing Hardware Using the SYM53C1010 2.7 Block Move and Chained Block Move Instructions 3.1 SYM53C1010-33 Functional Signal Grouping 4.1 Single Transition Transfer Waveforms 4.2 Double Transition Transfer Waveforms (XCLKS Examples) x Contents Target Timing Initiator Timing ...
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Double Transition Transfer Waveforms (XCLKH Examples) 5.1 SCRIPTS Overview 5.2 Block Move Instruction - First Dword 5.3 Block Move Instruction - Second Dword 5.4 Block Move Instruction - Third Dword 5.5 First 32-bit Word of the I/O Instruction 5.6 ...
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... Target Asynchronous Send 6.38 Target Asynchronous Receive 6.39 Initiator and Target ST Synchronous Transfer 6.40 Initiator and Target DT Synchronous Transfer 6.41 SYM53C1010-33 329 Ball Grid Array (Bottom View) 6.42 SYM53C1010-33 329 BGA Mechanical Drawing B.1 16 Kbyte Interface with 200 ns Memory B.2 64 Kbyte Interface with 150 ns Memory B.3 128, 256, 512 Kbyte or 1 Mbyte Interface with 150 ns Memory B ...
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... Default Download Mode Serial EEPROM Data Format 2.10 Power States 3.1 Left Half of the SYM53C1010-33 329 BGA Chip - Top View 3.2 Right Half of the SYM53C1010-33 329 BGA Chip - Top View 3.3 Signal Names and BGA Position 3.4 Signal Names by BGA Position 3.5 SYM53C1010 Internal Pull-ups and Pull-downs 3 ...
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LVD Driver SCSI Signals—SD[15:0], SDP[1:0], SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ 6-2 6.4 LVD Receiver SCSI Signals—SD[15:0], SDP[1:0], SREQ/, SACK/, SMSG/, SIO/, SCD/, SATN/, SBSY/, SSEL/, SRST/ 6-3 6.5 A and B DIFFSENS SCSI Signals 6.6 ...
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... Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or 40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock 6.49 Ultra2 SCSI Transfers 40.0 Mbyte (8-Bit Transfers) or 80.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock 6.50 Ultra3 SCSI Transfers 160.0 Mbyte (16-Bit Transfers) Quadrupled 40 MHz Clock A.1 SYM53C1010-33 PCI Register Map A.2 SYM53C1010-33 SCSI Register Map Contents 6-41 6-44 6-46 6-52 6-54 6-56 6-57 6-58 6-59 ...
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Contents ...
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... Transition (DT) clocking, Cyclic Redundancy Check (CRC), and Domain Validation. These features comply with the Ultra160 SCSI industry initiative. DT clocking permits the SYM53C1010 to transfer data up to 160 megabytes per second (Mbytes/s) on each channel for a total of 320 Symbios SYM53C1010-33 PCI to Dual Channel Ultra3 SCSI Multifunction Controller 1-1 ...
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... SYM53C1010 supports programming of local flash memory for BIOS updates. The chip is packaged in a 329 Ball Grid Array (BGA). shows a typical SYM53C1010 board application connected to external ROM or flash memory. Figure 1.1 Typical SYM53C1010-33 Board Application SCSI Data, Function A Parity, and 68 Pin Control Signals ...
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... Ultra3 SCSI standards. It implements multithreaded I/O algorithms with minimum processor intervention, solving the protocol overhead problems of previous intelligent and nonintelligent adapter designs. SYM53C1010 system application. Figure 1.2 Typical SYM53C1010-33 System Application PCI Bus PCI Bus Interface Controller Central Processing ...
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... New Features in the SYM53C1010-33 The SYM53C1010 is functionally similar to the SYM53C896 PCI to Dual Channel Ultra2 SCSI Multifunction Controller, with additional features and benefits. Following is a list of new SYM53C1010 features from the SYM53C896: Complies with PCI Rev. 2.2 specification Supports Ultra3 DT clocking for data transfers up to 160 Mbytes/s ...
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... Ultra3 speeds, allowing it to renegotiate to lower speed and bus width if necessary. SURElink is the software control for the manageability enhancements in the SYM53C1010 PCI to Dual Channel Ultra3 SCSI Multifunction Controller. Fully integrated in the SDMS™ software solution, SURElink provides Domain Validation at boot time as well as throughout system operation ...
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... For backward compatibility to existing SE devices, the SYM53C1010 features universal LVD Link transceivers that support LVD SCSI and SE SCSI. This allows use of the SYM53C1010 in both legacy and Ultra3 SCSI applications. 1.5 Benefits of TolerANT The SYM53C1010 features TolerANT technology, which includes active negation on the SCSI drivers and input signal fi ...
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... TolerANT technology is compatible with both the Alternative One and Alternative Two termination schemes proposed by the American National Standards Institute. 1.6 Summary of SYM53C1010-33 Benefits This section provides a summary of the SYM53C1010 features and benefits. It contains information on Integration, 1 ...
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Includes integrated LVD Link universal transceivers: – – – – Bursts 512 bytes across the PCI bus with an independent 896–920 byte FIFO on each SCSI channel. Includes two separate SCSI channels on one chip. Handles phase ...
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... Supports PCI Write and Invalidate, Read Line, and Read Multiple commands. Complies with PCI Bus Power Management Specification Rev 1.1. Complies with PC99. Summary of SYM53C1010-33 Benefits Can function in a 32-bit PCI slot Operates at 33 MHz Supports dual address cycle generation for all SCRIPTS ...
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... Integration The following features ease integration of the SYM53C1010 into a system: Dual channel Ultra3 SCSI PCI multifunction controller. Integrated LVD transceivers. Full 32-bit or 64-bit PCI DMA bus master. Memory-to-Memory Move instructions allow use as a third-party PCI bus DMA controller. Integrated SCRIPTS processor. ...
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... CRC and AIP provide end-to-end SCSI I/O protection ESD protection on SCSI signals. Protection against bus reflections due to impedance mismatches. Controlled bus assertion times (reduces RFI, improves reliability, and eases FCC certification). Latch-up protection greater than 150 mA. Summary of SYM53C1010-33 Benefits 1-11 ...
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... Power and ground isolation of I/O pads and internal chip logic. TolerANT technology provides: – – 1.6.7 Testability The following features enhance the testability of the SYM53C1010: All SCSI signals accessible through programmed I/O. SCSI bus signal continuity checking. Support for single-step mode operation. JTAG boundary scan. ...
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... The SYM53C1010-33 PCI to Dual Channel Ultra3 SCSI Multifunction Controller is composed of the following modules: 64-bit PCI Interface Two independent PCI to Wide Ultra3 SCSI Controllers ROM/Flash Memory Controller Serial EEPROM Controller Figure 2.1 Symbios SYM53C1010-33 PCI to Dual Channel Ultra3 SCSI Multifunction Controller illustrates the relationship between these modules. 2-1 ...
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... Figure 2.1 SYM53C1010-33 Block Diagram 64-Bit PCI Interface, PCI Configuration Registers (2 sets) Wide Ultra3 SCSI Channel 8 Dword SCRIPTS 8 Kbyte Prefetch Buffer SCRIPTS RAM SCSI FIFO and SCSI Control Block Universal TolerANT Drivers and Receivers JTAG JTAG SCSI Function A Interface Wide Ultra3 ...
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... PCI Configuration Register Map. At initialization time, each PCI device is assigned a base address for memory and I/O accesses. In the SYM53C1010, the upper 24 bits of the address are selected. On every access, the SYM53C1010 compares its assigned base addresses with the value on the Address/Data bus during the PCI address phase. If the upper 24 bits match, the access is designated for the SYM53C1010. The low order eight bits defi ...
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... SYM53C1010. which 256-byte I/O area this device occupies. 2.1.1.3 Memory Space The PCI specification defines memory space as a contiguous 64-bit memory address that is shared by all system resources. Register One (BAR1) (MEMORY) area this device occupies. Each SCSI function uses an 8 Kbyte SCRIPTS RAM memory space. ...
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... The SYM53C1010 does not respond to this command as a slave and it never generates this command as a master. 2.1.2.2 Special Cycle Command The SYM53C1010 does not respond to this command as a slave and it never generates this command as a master. PCI Functional Description PCI Bus Commands and Encoding Types ...
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... The SYM53C1010 uses the I/O Read command to read data from an agent mapped in the I/O address space. All 64 address bits are decoded. 2.1.2.4 I/O Write Command The SYM53C1010 uses the I/O Write command to write data to an agent mapped in the I/O address space. All 64 address bits are decoded. 2.1.2.5 Reserved Command The given bus encoding is reserved ...
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... This command is identical to the Memory Read command, except it additionally indicates that the master intends to fetch multiple cache lines before disconnecting. The SYM53C1010 supports PCI Memory Read Multiple functionality and issues Memory Read Multiple commands on the PCI bus when the Read Multiple mode is enabled. This mode is ...
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... The Read Line function in the SYM53C1010 takes advantage of the PCI 2.2 specification regarding issuance of this command. If the cache mode is disabled, no Read Line commands are issued. ...
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... The chip has enough bytes in the DMA FIFO to complete at least one full cache line burst. The chip is aligned to a cache line boundary. When these conditions are met, the SYM53C1010 issues a Write and Invalidate command instead of a Memory Write command during all PCI write cycles. ...
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... PCI specification. PCI Target Disconnect – If the target device issues a disconnect during a Memory Write and Invalidate transfer, the SYM53C1010 relinquishes the bus and immediately tries to finish the transfer on another bus ownership. The chip does not issue another Memory Write and Invalidate command on the next ownership unless the address is aligned ...
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... PCI bus. This ensures that no function is starved for access to the PCI bus. 2.1.4 PCI Cache Mode The SYM53C1010 supports the PCI specification for an 8-bit Size (CLS) Line Size (CLS) nonaligned addresses corresponding to cache line boundaries. In ...
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Not only must the above four conditions be met in order for the cache logic to control the type of PCI cache command that is issued, proper alignment is also necessary during write operations. If these conditions are not met ...
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Dword or cache boundary or if cache mode is not enabled a Memory Read command is issued. 2.1.4.4 Memory Write Caching Memory Writes are aligned in a single burst transfer to reach a cache boundary. At that ...
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Table 2.2 2-14 Functional Description PCI Cache Mode Alignment Host Memory 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 ...
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Examples MR = Memory Read, MRL = Memory Read Line, MRM = Memory Read, Multiple Memory Write, MWI = Memory Write and Invalidate. Read Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords: ...
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Read Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords Read Example ...
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Write Example 1 – Burst = 4 Dwords, Cache Line Size = 4 Dwords bytes (13 bytes (17 bytes bytes ...
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Write Example 2 – Burst = 8 Dwords, Cache Line Size = 4 Dwords Write Example ...
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... SCSI SCRIPTS, making it easy to “fine tune” the system for specific mass storage devices or Ultra3 SCSI requirements. the relationship between the SYM53C1010 modules. The SYM53C1010 offers low level register access or a high level control interface. Like first generation SCSI devices, the SYM53C1010 is accessed as a register-oriented device. The ability to sample and/or assert any signal on the SCSI bus is used in error recovery and diagnostic procedures ...
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... SCRIPTS instructions. These registers are described in detail in 2.2.2 Internal SCRIPTS RAM The SYM53C1010 has 8 Kbytes (2048 x 32 bits) of internal, general purpose RAM for each SCSI function. The RAM is designed for SCRIPTS program storage, but is not limited to this type of information. When the chip fetches SCRIPTS instructions or Table Indirect ...
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... SCSI SCRIPTS. For more information on the SCSI SCRIPTS instructions supported by the SYM53C1010, see SCRIPTS Instruction 2.2.3 64-Bit Addressing in SCRIPTS The PCI interface for the SYM53C1010 provides 64-bit address and data capability in the initiator mode. The chip can also respond to 64-bit addressing in the target mode. SCSI Functional Description ...
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... SYM53C1010 is not performing an EEPROM autodownload. The CON (Connected) bit in anytime the SYM53C1010 is connected to the SCSI bus either as an initiator or a target. This happens after the SYM53C1010 has successfully completed a selection or when it has successfully responded to a selection or reselection. It will also be set when the SYM53C1010 wins arbitration in low level mode ...
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... Designing an Ultra3 SCSI System Software modifications are needed to take advantage of the Ultra3 speed in the SYM53C1010. Since Ultra3 SCSI is based on existing SCSI standards, it can use existing drivers if they are able to negotiate for Ultra3 synchronous transfer rates. Also, the target device must be able to communicate at Ultra3 speed ...
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CRC – The error detecting code used in Ultra3 SCSI. Four bytes are transferred with data to increase the reliability of data transfers. CRC is used in the DT Data-In and DT Data-Out phases only. Because CRC is implied with ...
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Parallel Protocol Request (PPR) CRC, Sync/Wide, DT, QAS, and “information units” are negotiated with a new SCSI extended message: Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 Transfer Period Factor (Byte ...
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Note: The Table Indirect data (used during selection/reselection) must be updated to enable certain control bits in the register. Specific bits to look at include: bit 7, U3EN (Ultra3 Transfer Enable); bit 6, AIPEN (Asynchronous Information Protection Enable); and bits ...
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... SCSI Interrupt Status Zero (SIST0) CRC, or AIP errors are present. The LAIPERR bit in the (AIPCNTL1) 2.2.5.4 Register Considerations The following is a summary of the registers and bits required to enable Ultra3 SCSI on the SYM53C1010 device. The PCI The PCI it requires the bus every 4.5 s. The – ...
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The – – The – The – The – – – The – – – 2-28 Functional Description Bit 3, EWS (Enable Wide SCSI), is set to enable wide SCSI. Ultra3 requires wide SCSI. Therefore, this bit must ...
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Bit 3, XCLKH_DT (Extra Clock of Data Hold on DT Transfer Edge) is set to add a clock of data hold to synchronous DT SCSI transfers on the DT edge. – Bit 2, XCLKH_ST (Extra Clock of Data Hold ...
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... SPI-3 specification. Bit 6, DISCRC (Disable CRC protocol checking) causes the SYM53C1010 to not check for a CRC request prior to a phase change on the SCSI bus. This condition creates a SCSI error condition and makes the device noncompliant with the SPI-3 specifi ...
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... The – 2.2.5.5 Using the SCSI Clock Quadrupler The SYM53C1010 can quadruple the frequency MHz SCSI clock, allowing the system to perform Ultra3 SCSI transfers. This option is user selectable with bit settings in the Three (STEST3), and power-on or reset, the quadrupler is disabled and powered down. Follow these steps to use the clock quadrupler: 1 ...
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... SCRIPTS instructions, it uses the PCI cache commands Memory Read Line and Memory Read Multiple, if PCI caching is enabled. Note: To ensure the SYM53C1010 always operates from the current version of the SCRIPTS instruction, the contents of the prefetch unit may be flushed under certain conditions. The contents of the prefetch unit are automatically fl ...
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... Load and Store instructions, refer to SCRIPTS Instruction SCSI Functional Description (DMA Control (DCNTL) register (0x38) causes the SYM53C1010 to burst in the first This feature is only useful if Prefetching is disabled. This feature is only useful if fetching SCRIPTS instructions from main memory. Due to the short access time of SCRIPTS RAM, burst opcode fetching is not necessary when fetching instructions from SCRIPTS RAM ...
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... SCRIPTS RAM must first be written before being read in order to initialize SCRIPTS RAM parity SCRIPTS RAM parity error is encountered, a SCSI Gross Error interrupt will be signaled. The SYM53C1010 supports CRC checking and generation in DT phases and CRC checking and generation during DT Data Transfers. The new CRC registers are ...
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Parity/CRC/AIP Error or ATN), and bit 0, (SCSI Parity/CRC/AIP Error). The new AIP registers are SCSI Control Zero Zero (AIPCNTL0), and AIP Control One SCSI Functional Description SCSI Interrupt Enable Zero (SCNTL0), AIP Control (AIPCNTL1). (SIEN0), 2-35 ...
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... Data Latch (SIDL) This bit enables parity checking during PCI master data phases. This bit is set when the SYM53C1010 PCI master, detects a target device signaling a parity error during a data phase. By clearing this bit, a Master Data Parity Error does not ...
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... This bit is set to cause the device to not check for a CRC request prior to a phase change on the SCSI bus. This condition normally causes a SCSI error condition. Note: Setting this bit makes the SYM53C1010 noncompliant to the SPI-3 specification. This bit should not be set under normal operating conditions. ...
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... DMA transfers. The FIFO allows the SYM53C1010 to support 4, 8, 16, 32, 64, or 128 Dword bursts across the PCI bus interface. 2.2.12 SCSI Data Paths The data path through the SYM53C1010 is dependent on whether data is moved into or out of the chip and whether the SCSI data transfer is asynchronous or synchronous. ...
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... Figure 2.3 SYM53C1010 Host Interface SCSI Data Paths Asynchronous Asynchronous SCSI Send SCSI Receive PCI Interface PCI Interface DMA FIFO DMA FIFO SODL Register SIDL Register SCSI Interface SCSI Interface 2.2.12.1 Asynchronous SCSI Send To determine the number of bytes remaining in the DMA FIFO when a phase mismatch occurs, read the register ...
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... DMA FIFO should be cleared by setting bit 2 (CLF) in (CTEST3), the SCSI FIFO should be cleared by setting bit 1 (CSF) in SCSI Test Three 2.2.13 SCSI Bus Interface The SYM53C1010 performs SE and LVD transfers. 2-40 Functional Description register. This 16-bit, read only register contains the Chip Test Three (CTEST3) and the I/O should be retried ...
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... For information on terminators that support LVD, refer to the SPI-3 draft standard. Note: SCSI Functional Description register and bit 5 (DIF) of the pull-up resistor to the terminator power If the SYM53C1010 is used in a design with an 8-bit SCSI bus, all 16 data lines must be terminated. SCSI Status Two SCSI Test Two (STEST2) register pull-down resistor to ground. ...
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... Once a change in operating mode occurs, either the initiator SCRIPTS issues a Set Initiator instruction or the target SCRIPTS issues a Set Target instruction. The Selection and Reselection Enable bits ID (SCID) the SYM53C1010 to respond as an initiator target. If only selection is enabled, the SYM53C1010 cannot be reselected as an 2-42 Functional Description ...
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... The SYM53C1010 can receive data from the SCSI bus at a synchronous transfer period as short as 12.5 ns, regardless of the transfer period used to send data. The SYM53C1010 can receive data at one-fourth of the divided SCLK frequency. Depending on the SCLK frequency, the negotiated transfer period, and the synchronous clock divider, the SYM53C1010 can send synchronous data at intervals as short as 12 ...
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... This bit impacts DT and ST transfers as it affects data hold to the ST edge. Setting this bit reduces the synchronous transfer send rate but will not reduce the rate at which the SYM53C1010 receives outbound REQs, ACKs, or data. Bit 1, XCLKS_DT (Extra Clock of Data Setup on DT transfer edge), adds a clock of data setup to synchronous DT SCSI transfers on the DT edge ...
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... To configure the SYM53C1010 for Ultra3 DT transfers, perform the following steps: Step 1. Enable the SCSI Clock Quadrupler – The SYM53C1010 can quadruple the frequency MHz SCSI clock, allowing the system to perform Ultra3 SCSI transfers. This option is user selectable through bit settings in the register ...
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... Step 4. Enable TolerANT – Set the TolerANT Enable bit, An example of configuring the Ultra3 SCSI transfer speed is: 1. Set SCNTL3 to 0x18. 2. Set SXFER to 0x3E. 3. Set SCNTL4 to 0x80. These settings program the SYM53C1010 SCSI clocks to send and receive at 160 MHz with a synchronous SCSI offset of 0x3E. 2-46 Functional Description (SCNTL3) ...
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... The SCRIPTS processors in the SYM53C1010 perform most functions independently of the host microprocessor. However, certain interrupt situations must be handled by the external microprocessor. This section explains all aspects of interrupts as they apply to the SYM53C1010. 2.2.16.1 Polling and Hardware Interrupts The external microprocessor is informed of an interrupt condition by polling or hardware interrupts ...
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... SCSI Function A is routed to PCI Interrupt INTA/. SCSI Function B is normally routed to INTB/, but can be routed to INTA pull-up is connected to MAD[4]. See additional information. 2.2.16.2 Registers The registers in the SYM53C1010 used for detecting or defining interrupts are One (SIST1), SCSI Interrupt Enable One See the register descriptions in information ...
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... SIST0 and SIST1, and clears the SIP bit in Interrupt Status Zero (ISTAT0). Since the SYM53C1010-33 SCSI functions stack interrupts, SIST0 and SIST1 are not necessarily cleared after a read; additional interrupts may still be pending. If the SYM53C1010 is receiving data from the SCSI bus and a fatal interrupt condition occurs, the chip attempts to send the contents of the DMA FIFO to memory before generating the interrupt ...
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... Functional Description Chip Test Three (CTEST3) SCSI Test Three (STEST3) DMA Status (DSTAT) (ISTAT0). Since the SYM53C1010-33 SCSI DMA Status (DSTAT), DFE, is purely a status bit; it will not SCSI Interrupt Enable Zero (SIEN0) registers are the interrupt enable registers SCSI Interrupt Status Zero (SIST0) (SIST1) ...
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... CPU. This prevents an interrupt when arbitration is complete (CMP set), when the SYM53C1010 is selected or reselected (SEL or RSL set), when the initiator asserts ATN (target mode: SATN/ active), or when the General Purpose or Handshake-to-Handshake timers expire. These interrupts are not needed for events that occur during high level SCRIPTS operation ...
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... Interrupt Status Zero (ISTAT0) the INTA/ (or INTB/) pin. 2.2.16.5 Stacked Interrupts The SYM53C1010 will stack interrupts, if they occur, one after the other. If the SIP or DIP bits in the set (first level), there is already at least one pending interrupt. Any future interrupts are stacked in extra registers behind the ...
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... These ‘locked out’ SCSI interrupts are posted as soon as the DMA FIFO is empty. 2.2.16.6 Halting in an Orderly Fashion When an interrupt occurs, the SYM53C1010 attempts to halt in an orderly fashion. If the interrupt occurs in the middle of an instruction fetch, the fetch is completed, except in the case of a Bus Fault. Execution does not begin, but the DSP points to the next instruction since it is updated when the current instruction is fetched ...
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... All other instructions may halt before completion. 2.2.16.7 Sample Interrupt Service Routine The following is a sample of an Interrupt Service Routine (ISR) for the SYM53C1010. It can be repeated if polling is used, or should be called when the INTA/ (or INTB/) pin is asserted if hardware interrupts are used. 1. Read 2. If the INTF bit is set, write one to clear this status. ...
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... ISR. 2.2.17 Interrupt Routing This section documents the recommended approach to RAID ready interrupt routing for the SYM53C1010. In order to be compatible with RAID upgrade products and the SYM53C1010, the following requirements must be met: When a RAID upgrade card is installed in the upgrade slot, interrupts ...
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... As long as the interrupt routing requirements stated above are satisfied, a motherboard designer could implement this design with external logic. Figure 2.6 Interrupt Routing Hardware Using the SYM53C1010 + SYM53C1010 2.7 K ALT_INTA/ SCSI Core INTA/ A ALT_INTB/ ...
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... BIOS and assumes the operating system uses PCI BIOS calls when searching for PCI devices. 2.2.18 Chained Block Moves Since the SYM53C1010 has the capability to transfer 16-bit wide SCSI data, a unique situation occurs when dealing with odd bytes. The Chained Move (CHMOV) SCRIPTS instruction along with the Wide SCSI ...
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Wide SCSI Receive Bit The WSR bit is set following a wide SCSI receive operation (Data-In for initiator mode or Data-Out for target mode) when the SCSI core is holding a byte of chain data. The SCSI core holds ...
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Move instruction facilitates partial receive transfers and allows correct partial send behavior without additional opcode overhead. Behavior of the chained Block Move instruction varies slightly for sending and receiving data. For receive data (Data-In for the initiator or Data-Out for ...
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... The data in address 0x09 is married with the stored data (0x07) and transferred to the SCSI bus. 2.3 Parallel ROM Interface The SYM53C1010 supports Mbyte of external memory in binary increments from 16 Kbytes to allow the use of expansion ROM for add- in PCI cards. Both functions of the device share the ROM interface. This ...
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... Reset signal and configures the Address (ERBA) register and the memory cycle state machines for the appropriate conditions. The SYM53C1010 supports a variety of sizes and speeds of expansion ROM. An example set of interface drawings is in Memory Interface Diagram Examples”. The encoding of pins MAD[3:1] allows the user to defi ...
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... For example, to connect Kbytes external ROM use a pull-up on MAD[2]. If the external memory interface is not used, MAD[3:1] should be pulled high. The SYM53C1010 allows the system to determine the size of the available external memory using the (ERBA) how this works, refer to the PCI specification or the Expansion ROM Base Address register description in MAD[0] is the slow ROM pin ...
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... ID (SVID) value of 0x1000 and 0x1000 respectively. 2.5 Power Management The SYM53C1010 complies with the PCI Bus Power Management Interface Specification, Revision 1.1. The PCI Function Power States D0, D1, D2, and D3 are defined in that specification the maximum powered state, and D3 is the minimum powered state ...
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... Power state D0 is the maximum power state and is the power-up default state for each function. The SYM53C1010 is fully functional in this state. 2.5.2 Power State D1 Power state lower power state than D0. A function in this state places the SYM53C1010 core in the snooze mode and the SCSI clock 2-64 Functional Description Power States ...
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... D0 by applying V Power state lower power level than power state D2. A function in this state places the SYM53C1010 core in the coma mode. Furthermore, the function's soft reset is continually asserted while in power state D3, which clears all pending interrupts and 3-states the SCSI bus. In ...
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Functional Description ...
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... Test Interface Figure 3.1 slash (/) at the end of a signal name indicates that active LOW signal. When the slash is absent, the signal is active at a HIGH voltage. Symbios SYM53C1010-33 PCI to Dual Channel Ultra3 SCSI Multifunction Controller illustrates the signals, their grouping, and their I/O direction. A 3-1 ...
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The PCI Interface contains many functional groups of signals. The SCSI Bus Interface contains two functional groups of signals as illustrated in Figure 3.1. There are five signal type definitions: I Input, a standard input-only signal. O Output, a standard ...
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... Figure 3.1 SYM53C1010-33 Functional Signal Grouping System Address and Data Interface Control Arbitration PCI Bus Interface Error Reporting Interrupt SCSI Function A GPIO SCSI Function B GPIO Flash ROM and Memory Interface Signal Organization SYM53C1010-33 CLK SCLK RST/ A_SD[15:0]/ A_SDP[1:0]/ AD[63:0] A_DIFFSENS C_BE[7:0]/ PAR PAR64 ...
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... Table 3.1 Left Half of the SYM53C1010-33 329 BGA Chip - Top View TEST_PD A_SD12+ A_SD13 A_SD13 DD C TEST_ _IO A_SD12 SS SS RST/ D TCK _IO CORE CORE E TDO TDI TMS CORE F ALT_ INTB INTA/ ...
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... Table 3.2 Right Half of the SYM53C1010-33 329 BGA Chip - Top View A_SACK+ A_SMSG+ A_SC_D A_SRST A_SSEL NC C A_SACK A_SMSG A_SC_D A_SREQ D A_SRST+ V _IO A_SSEL _IO V _IO _IO V _IO _IO V _IO ...
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Table 3.3 Signal Names and BGA Position Signal BGA Signal Name Pos Name AD4 A_DIFFSENS A20 AD5 A_GPIO0_ AD6 FETCH/ AB16 AD7 A_GPIO1_ AD8 MASTER/ Y16 AD9 A_GPIO2 AA16 AD10 A_GPIO3 AC17 AD11 A_GPIO4 AB17 AD12 A_SACK C13 AD13 A_SACK+ ...
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Table 3.4 Signal Names by BGA Position Signal BGA Signal Name Pos Name MAD4 NC A1 MAD1 TEST_PD A2 NC A_SD12 _CORE A_SD13 _CORE A_SD15 _CORE A_SD0 C_BE6/ A_SD2 A7 ...
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... Internal Pull-ups and Pull-downs on SYM53C1010 Signals Several SYM53C1010 signals use internal pull-ups and pull-downs. 3.5 describes the conditions that enable these pull-ups and pull-downs. Table 3.5 SYM53C1010 Internal Pull-ups and Pull-downs Pull-up Pin Name Current INTA/, INTB/, ALT_INTA ALT_INTB/ INT_DIR, TCK, TDI, ...
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PCI Bus Interface Signals The PCI Bus Interface Signals section contains tables describing the signals for the following signal groups: Data Signals, Reporting SCSI Function B GPIO 3.3.1 System Signals Table 3.6 Table 3.6 System Signals Name Bump Type ...
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Address and Data Signals Table 3.7 Table 3.7 Address and Data Signals Name Bump AD[63:0] Y5, AB5, AC5, AA6, Y6, AB6, AC6, AA7, AB7, AC7, AA8, Y8, AB8, AC8, AA9, Y9, AB9, AC9, AA10, Y11, AB10, AC10, AA11, AC11, ...
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Table 3.7 Address and Data Signals (Cont.) Name Bump PAR64 AA5 3.3.3 Interface Control Signals Table 3.8 Table 3.8 Interface Control Signals Name Bump Type Strength Description ACK64/ AB1 S/T PCI Acknowledge 64-bit transfer is driven by the ...
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Table 3.8 Interface Control Signals (Cont.) Name Bump Type Strength Description STOP/ R2 S/T PCI Stop indicates that the selected target is requesting the DEVSEL/ R1 S/T PCI Device Select indicates that the driving device has ...
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Error Reporting Signals Table 3.10 Table 3.10 Error Reporting Signals Name Bump Type Strength Description PERR/ R4 S/T PCI Parity Error may be pulsed active by an agent that detects SERR PCI System ...
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... SCSI Test One (STEST1) about disabling this interrupt in a RAID environment. At power-up, this interrupt can be rerouted to INTA/ using the INTA/ enable sense resistor (pull-up on MAD4). This causes the SYM53C1010 to program the SCSI Function B PCI Interrupt Pin (IP) SCSI Test One (STEST1) for register to 0x01 ...
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... MAD7 pin, to serve as the clock signal for the serial EEPROM interface. If bit 7 of the General Purpose Pin Control (GPCNTL) set, this pin drives low when the SYM53C1010 is the bus master SCSI Function A General Purpose I/O pin 2. This pin powers input ...
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... MAD7 pin to serve as the clock signal for the serial EEPROM interface. If bit 7 of the General Purpose Pin Control (GPCNTL) this pin is driven low when the SYM53C1010 is the bus master SCSI Function B General Purpose I/O pin 2. This pin powers input ...
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SCSI Bus Interface Signals The SCSI Bus Interface Signals section contains tables describing the signals for the following signal groups: Function A signals and SCSI Function B signals each have a subgroup: the Function A Control Signals Table 3.14 ...
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Table 3.15 SCSI Function A Signals (Cont.) Name Bump A_SDP[1:0] C6, A10. A_SDP[1:0]+ D6, C11. A_DIFFSENS A20 3-18 Signal Descriptions Type Strength Description I/O SE: SCSI Function A Parity SCSI LVD Mode: Negative half of the LVD Link ...
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Table 3.16 SCSI Function A Control Signals 1 Name Bump Type Strength SCSI Function A Control includes the following signals: A_SC_D C15 I/O SE SCSI A_SC_D+ A16 LVD UniLVD A_SI_O B17 A_SI_O+ C17 A_SMSG C14 A_SMSG+ ...
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SCSI Function B Signals This section describes the SCSI Function B Signals group divided into two tables: 3.18 describes SCSI Function B Control Signals. Table 3.17 SCSI Function B Signals Name Bump B_SD[15:0] F21, E22, E21, D22, ...
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Table 3.17 SCSI Function B Signals (Cont.) Name Bump B_SDP[1:0]+ F23, L22. B_DIFFSENS Y21 SCSI Bus Interface Signals Type Strength Description I/O SE: SCSI Function B Parity SCSI LVD Mode: Positive half of the LVD Link pair for ...
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Table 3.18 SCSI Function B Control Signals 1 Name Bump Type SCSI Function B Control includes the following signals: B_SC_D T20 I/O B_SD_D+ T21 LVD UniLVD B_SI_O V22 B_SI_O+ V20 B_SMSG R20 B_SMSG+ R21 B_SREQ U21 B_SREQ+ V23 ...
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... Memory Address Strobe 1. This pin is used to latch in the most significant address byte (bits [15:8 external EPROM or flash memory. Since the SYM53C1010 moves addresses eight bits at a time, this pin connects to the clock of an external bank of flip-flops that assemble 20-bit address for the external memory ...
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... Memory Output Enable. This pin is used as an output enable signal to an external EPROM or flash memory during read operations also used to test the connectivity of the SYM53C1010 signals in the “AND-tree” test mode. N/A Test Clock. This pin provides the clock for the JTAG test logic ...
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Power and Ground Signals Table 3.21 Table 3.21 Power and Ground Signals 1 Name Bump V C3, C21, D4, D12, SS_IO D20, K10–14, L10–14, M4, M10–14, M20, N10–14, P10–14, Y4, Y12, Y20, AA3, AA21. V D7, D10, D14, D17, ...
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MAD Bus Programming The MAD[7:0] pins, in addition to serving as the address/data bus for the local memory interface, also are used to program power-up options for the chip. A particular option is programmed allowing the internal pull- down ...
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MAD[3:1] pins – These pins set the size of the external expansion ROM device attached. The encoding for these pins is listed in the following table. A “0” indicates a pull-down resistor is attached while a “1” indicates a pull-up ...
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Signal Descriptions ...
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... ID, Command, and PCI-compliant registers is optional. In the SYM53C1010, registers that are not supported are not writable and return all zeros when read. Only Symbios SYM53C1010-33 PCI to Dual Channel Ultra3 SCSI Multifunction Controller shows the PCI configuration registers implemented in the Status registers. Support of other Interrupt Pin (IP) register ...
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... SYM53C1010 are described in this chapter. Do not access bits marked as Reserved. Table 4.1 PCI Configuration Register Map 31 Device ID Status Class Code (CC) Reserved Header Type (HT) Base Address Register Zero (BAR0) (I/O) Base Address Register One (BAR1) (MEMORY) ...
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... This 16-bit register identifies the manufacturer of the device. The Vendor ID is 0x1000. Registers: 0x02–0x03 Device ID Read Only DID Device ID This 16-bit register identifies the particular device. The SYM53C1010-33 Device ID is 0x0020. Registers: 0x04–0x05 Command Read/Write The SCSI Command register provides coarse control over a device’ ...
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... This bit controls the ability of the SYM53C1010 to act as a master on the PCI bus. A value of zero disables this device from generating PCI bus master accesses. A value of one allows the SYM53C1010 to behave as a bus master. The device must be a bus master to fetch SCRIPTS instructions and transfer data. ...
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... DPE Detected Parity Error (from Slave) This bit is set by the SYM53C1010 upon the detection of a data parity error, even if data parity error handling is disabled. SSE Signaled System Error This bit is set whenever the device asserts the SERR/ signal ...
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... These bits are read only and indicate the slowest time that a device asserts DEVSEL/ for any bus command except Configuration Read and Configuration Write. The SYM53C1010 supports a value of 0b01. Data Parity Error Reported This bit is set when the following conditions are met: The bus agent asserts PERR/ itself or observes PERR/ asserted and ...
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Register: 0x08 Revision ID (RID) Read Only 7 x RID Registers: 0x09–0x0B Class Code (CC) Read Only Register: 0x0C Cache Line Size (CLS) Read/Write 7 0 CLS PCI Configuration Registers ...
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... The Latency Timer register specifies, in units of PCI bus clocks, the value of the Latency Timer for this PCI bus master. The SCSI functions of the SYM53C1010 support this timer. All eight bits are writable, allowing latency values of 0–255 PCI clocks. Use the following equation to calculate an optimum latency value for the SCSI functions of the SYM53C1010 ...
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... Base Address Register Zero - I/O This base address register is used to map the operating register set into I/O space. The SYM53C1010 requires 256 bytes of I/O space for this base address register. Bit 0 is hardwired to one. Bit 1 is reserved and returns a zero on all reads. All other bits are used to map the device into I/O space. For detailed information on the operation of this register, refer to the PCI 2.2 specifi ...
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... Address Register One (BAR1) operating registers into memory space and represents the upper 32 bits of the memory address. The default value of this register is 0x00000000. The SYM53C1010 requires 1024 bytes of memory space. For detailed information on the operation of this register, refer to the PCI 2.2 specification. ...
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... SCRIPTS RAM into memory space and represents the lower 32 bits of the memory address. Bits [12:0] are hardwired to 0b0000000000100. The default value of this register is 0x00000004. The SYM53C1010 requires 8192 bytes of memory space for SCRIPTS RAM. For detailed information on the operation of this register, refer to the PCI 2.2 specifi ...
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Registers: 0x24–0x27 Reserved This register is reserved. Registers: 0x28–0x2B Reserved This register is reserved. Registers: 0x2C–0x2D Subsystem Vendor ...
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EEPROM or, if the download fails, a value of 0x0000. If the external serial EEPROM interface is disabled (MAD[7] HIGH), this register returns a value of 0x1000. The 16-bit value that should be stored ...
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... ROM Base Address (ERBA) and then reading back the register. The SCSI functions of the SYM53C1010 respond with zeros in all don’t care locations. The least significant one that remains represents the binary version of the external memory size ...
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Register: 0x34 Capabilities Pointer (CP) Read Only Registers: 0x35–0x37 Reserved This register is reserved. Registers: 0x38–0x3B Reserved This register is reserved. PCI ...
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Register: 0x3C Interrupt Line (IL) Read/Write Register: 0x3D Interrupt Pin (IP) Read Only Note: 4-16 Registers Interrupt Line This register is used to communicate interrupt line routing ...
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... Max_Lat is used to specify how often the device needs to gain access to the PCI bus. The value specified in this register is in units of 0.25 microseconds. The SYM53C1010 SCSI function sets this register to 0x12 indicating it needs the bus every 4 maintain a data stream of 160 Mbytes/s. ...
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... D2S D1S AUX_C PME_Support Bits [15:11] define the power management states in which the SYM53C1010 will assert the PME pin. These bits are all set to zero because the SYM53C1010 does not provide a PME signal [7: [7:0] ...
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... R Reserved PMEC PME Clock Bit 3 is cleared because the SYM53C1010 does not provide a PME pin. VER[2:0] Version These three bits are set to 0b010 to indicate that the SYM53C1010 complies with Revision 1.1 of the PCI Power Management Interface Specifi ...
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... Therefore, these two bits are always cleared. Data_Select The SYM53C1010 does not support the Therefore, these four bits are always cleared. PME_Enable The SYM53C1010 always returns zero for this bit to indicate that PME assertion is disabled. Reserved Power State Bits [1:0] are used to determine the current power state of the SYM53C1010 ...
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... Register: 0x46 Bridge Support Extensions (PMCSR_BSE) Read Only BSE Bridge Support Extensions This register indicates PCI Bridge specific functionality. The SYM53C1010 always returns 0x00. Register: 0x47 Data Read Only DATA Data This register provides an optional mechanism for the function to report state-dependent operating data ...
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... Updated Address (UA), (IA), SCSI Byte Count (CSBC). All the phase mismatch registers The only registers that the host CPU can access while the SYM53C1010 is executing SCRIPTS are the tus Zero (ISTAT0), Interrupt Status One Zero (MBOX0), and Mailbox One (MBOX1) attempts to access other registers interfere with the operation of the chip ...
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Table 4.2 SCSI Register Map SCNTL3 SCNTL2 GPREG SDID SBCL SSID SSTAT2 SSTAT1 MBOX1 MBOX0 CTEST3 CTEST2 CTEST6 CTEST5 DCMD DCNTL SBR SIST1 SIST0 GPCNTL Reserved RESPID1 RESPID0 STEST3 STEST2 CSO STEST4 CCNTL1 CCNTL0 CCNTL3 Reserved SCRATCH ...
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... Full arbitration, selection/reselection Simple Arbitration 1. The SYM53C1010 SCSI function waits for a bus free condition to occur asserts SBSY/ and its SCSI ID, contained in the SCSI Chip ID (SCID) the SSEL/ signal is asserted by another SCSI device, the SYM53C1010 SCSI function deasserts SBSY/, deasserts its ID, and sets the Lost Arbitration ...
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... Full Arbitration, Selection/Reselection 1. The SYM53C1010 SCSI function waits for a bus free condition asserts SBSY/ and its SCSI ID onto the SCSI bus. The SCSI ID asserted is the highest priority ID stored in the 3. If the SSEL/ signal is asserted by another SCSI device or if the SYM53C1010 SCSI function detects ...
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... When this bit is clear, parity and CRC errors are not reported. CRC Request Pending When this bit is set, the SYM53C1010 SCSI function has an outstanding CRC request pending. When this bit is set and the SYM53C1010 is in target mode, a Block Move SCSI Interrupt Status SCSI Interrupt Status Zero ...
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... This is done using the SCRIPTS language (SET TARGET or CLEAR TARGET). When this bit is set, the chip is a target device. When this bit is cleared, the SYM53C1010 SCSI function is an initiator device. Caution: Writing this bit while not connected may cause the loss of a selection or reselection due to the changing of target or initiator modes ...
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... If the SYM53C1010 SCSI function is receiving data, any data residing in the DMA FIFO is sent to memory before halting. When this bit is set, the SYM53C1010 SCSI function does not halt the SCSI transfer when SATN Parity/CRC/AIP error is received. 3 ...
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... Connected This bit is automatically set any time the SYM53C1010 SCSI function is connected to the SCSI bus as an initiator target set after the SYM53C1010 SCSI function successfully completes arbitration or when it has responded to a bus-initiated selection or reselection. This bit is also set after the chip wins simple arbitration when operating in low level mode ...
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... SCSI bus not acceptable the Bus Free phase immediately following the arbitration phase possible to perform a low level selection instead. The abort completes because the SYM53C1010 SCSI function loses arbitration. This is detected by the clearing of the Immediate Arbitration bit. Do not use the Lost Arbitration bit bit 3) to detect this condition ...
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Abort, Abort Tag, Bus Device Reset, Clear Queue or Release Recovery message, or before deasserting SACK/ after receiving a Disconnect command or Command Complete message. CHM Chained Mode This bit ...
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Register: 0x03 SCSI Control Three (SCNTL3) Read/Write This register is automatically loaded when a Table Indirect Select or Reselect SCRIPTS instruction is executed. R SCF[2:0] EWS 4-32 Registers For more information refer to Block Moves.” ...
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... SRE Reserved RRE Enable Response to Reselection When this bit is set, the SYM53C1010 SCSI function is enabled to respond to bus-initiated reselection at the chip ID in the Response ID Zero (RESPID0) One (RESPID1) automatically reconfigure itself to the initiator mode as a result of being reselected. SRE ...
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... Reserved Max SCSI Synchronous Offset These bits describe the maximum SCSI synchronous offset used by the SYM53C1010 SCSI function when transferring synchronous SCSI data in either the initiator or target mode. Table 4.3 combinations and their relationship to the synchronous data offset used by the SYM53C1010 SCSI function. ...
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A value these bits program the device to perform asynchronous transfers. A value of 1 during DT transfers is illegal and will result in data corruption. Table 4.3 Maximum Synchronous Offset MO5 MO4 MO3 MO2 0 0 ...
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Register: 0x07 General Purpose (GPREG) Read/Write write to this register will cause the data written to be output to the appropriate GPIO pin set to output mode in that function’s Purpose Pin Control (GPCNTL) ...
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... SCSI First Byte Received This register contains the first byte received in any asynchronous information transfer phase. For example, when a SYM53C1010 SCSI function is operating in the initiator mode, this register contains the first byte received in the Message-In, Status, and Data-In phases. When a Block Move instruction is executed for a particular phase, the fi ...
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... It is controlled by the SCRIPTS processor when executing SCSI SCRIPTS. transferring data using programmed I/O. Some bits are set or cleared when executing SCSI SCRIPTS. Do not write to the register once the SYM53C1010 SCSI function starts executing normal SCSI SCRIPTS. REQ ACK BSY SEL ...
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... ENID Encoded Destination SCSI ID Reading the SSID register immediately after the SYM53C1010 SCSI function is selected or reselected returns the binary-encoded SCSI ID of the device that performed the operation. These bits are invalid for targets that are selected under the single initiator option of the SCSI-1 specifi ...
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... DMA Status (DSTAT) Read Only 7 DFE 1 Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register in case additional interrupts are pending (the SYM53C1010 SCSI functions stack 4-40 Registers ACK BSY ...
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... Parity Error Enable bit (bit Bus Fault This bit is set when a PCI bus fault condition is detected. A PCI bus fault can only occur when the SYM53C1010 SCSI function is bus master, and is defined as a cycle that ends with a Bad Address or Target Abort Condition. ABRT Aborted This bit is set when an abort condition occurs ...
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... SYM53C1010 SCSI function is operating in single-step mode or automatically executing SCSI SCRIPTS. Any of the following conditions during instruction execution also sets this bit: The SYM53C1010 SCSI function is executing a Wait Disconnect instruction and the SCSI REQ line is asserted without a disconnect occurring. A Block Move instruction is executed as an initiator ...
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A Load and Store instruction attempts to cross a Dword boundary. A Memory Move instruction is executed with one of the reserved bits in the register set. A Memory Move instruction is executed with the source and destination addresses not ...
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... SCSI bus, and lost arbitration due to another SCSI device asserting the SSEL/ signal. Won Arbitration When set, WOA indicates that the SYM53C1010 SCSI function has detected a Bus Free condition, arbitrated for the SCSI bus and won arbitration. The arbitration mode ...
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Register: 0x0E SCSI Status One (SSTAT1) Read Only Reserved SDP0L Latched SCSI Parity This bit reflects the SCSI parity signal (SDP0/), corresponding to the data latched in the Latch (SIDL). It changes when a ...
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Register: 0x0F SCSI Status Two (SSTAT2) Read Only 7 ILF1 0 ILF1 R OLF1 R SPL1 R LDSC 4-46 Registers OLF1 R SPL1 SIDL Most Significant Byte Full This bit is ...
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... Read this register after servicing an interrupt to check for stacked interrupts. SCSI Registers SYM53C1010 SCSI function. If the Connected bit and the LDSC bit are asserted, a disconnect is indicated. This bit is set when the Connected bit in SCNTL1 is off. This bit is cleared when a Block Move instruction is executed while the Connected bit in SCNTL1 is set ...
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... Software Reset Setting this bit resets the SYM53C1010 SCSI function. All operating registers are cleared to their respective default values and all SCSI signals are deasserted. Setting this bit does not assert the SCSI RST/ signal. This reset does not clear the ID Mode bit or any of the PCI confi ...
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... Semaphore The SCRIPTS processor may set this bit using a SCRIPTS register write instruction. An external processor may also set it while the SYM53C1010 SCSI function is executing a SCRIPTS operation. This bit enables the SCSI function to notify an external processor of a predefined condition while SCRIPTS are running. The external processor may also notify the SYM53C1010 SCSI function of a predefi ...
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... After it has been set, this bit must be written to one to clear it. SCSI Interrupt Pending This status bit is set when an interrupt condition is detected in the SCSI portion of the SYM53C1010 SCSI function. The following conditions cause a SCSI interrupt to occur: A phase mismatch (initiator mode) or SATN/ becomes ...
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An illegal instruction is detected To determine exactly which condition(s) caused the interrupt, read the Register: 0x15 Interrupt Status One (ISTAT1) Read/Write Reserved FLSH Flushing If this bit is set, the chip is flushing ...
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Register: 0x16 Mailbox Zero (MBOX0) Read/Write 7 0 MBOX0 Note: Register: 0x17 Mailbox One (MBOX1) Read/Write 7 0 MBOX1 Note: 4-52 Registers MBOX0 Mailbox Zero These are general purpose bits that may be read or written ...
Page 175
Register: 0x18 Chip Test Zero (CTEST0) Read/Write FMT Byte Empty in DMA FIFO These bits identify the lower bytes in the DMA FIFO that are empty. Each bit corresponds to a byte lane in the DMA ...
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Register: 0x1A Chip Test Two (CTEST2) Read Only (bit 3 write SIGP CIO CM Note: PCICIE 4-54 Registers SIGP CIO CM PCICIE Reserved Signal Process This bit is a copy ...
Page 177
... Next Address (DNAD) signal, controlled by the register, determines the direction of the transfer. This bit is not self-clearing; clear it once the data is successfully transferred by the SYM53C1010 SCSI function. Note: Polling of FIFO flags is allowed during flush operations. SCSI Registers Base Address and RAM) ...
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... Return instruction is executed. This address points to the next instruction to execute. Do not write to this register while the SYM53C1010 SCSI function is executing SCRIPTS. During any Memory-to-Memory Move operation, the contents of this register are preserved. The power-up value of this register is indeterminate. ...
Page 179
Register: 0x20 Reserved This register is reserved. Register: 0x21 Chip Test Four (CTEST4) Read/Write FBL3 Reserved FBL3 FIFO Byte Control 3 This bit is used with FBL[2:0]. ...
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... SYM53C1010 SCSI function is informed of the error by the PERR/ pin being asserted by the target. When this bit is cleared, the SYM53C1010 SCSI function does not interrupt if a master parity error occurs. This bit is cleared at power-up. ...
Page 181
Register: 0x22 Chip Test Five (CTEST5) Read/Write ADCK BBCK ADCK Clock Address Incrementor Setting this bit increments the address pointer contained in the DMA Next Address (DNAD) register is incremented based on the DNAD ...
Page 182
Register: 0x23 Chip Test Six (CTEST6) Read/Write 4-60 Registers DMA FIFO Writing to this register writes data to the appropriate byte lane of the DMA FIFO, as determined by the FBL bits ...
Page 183
... Counter (DBC) register is 0xFFFFFF. If the instruction is a Block Move and a value of 0x000000 is loaded into the DBC register, an illegal instruction interrupt occurs if the SYM53C1010 SCSI function is not in the target mode, Command phase. The DMA Byte Counter (DBC) hold the least significant 24-bits of the first Dword of a SCRIPTS fetch, and to hold the offset value during Table Indirect I/O SCRIPTS ...
Page 184
... DNAD 4-62 Registers DCMD DMA Command This 8-bit register determines the instruction for the SYM53C1010 SCSI function to execute. This register has a different format for each instruction. For a complete description see Chapter 5, “SCSI SCRIPTS Instruction Set”. DNAD ...
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Registers: 0x2C–0x2F DMA SCRIPTS Pointer (DSP) Read/Write DSP Registers: 0x30–0x33 DMA SCRIPTS Pointer Save (DSPS) Read/Write DSPS SCSI ...
Page 186
... This value is also independent of the width (64-bit or 32-bit) of the data transfer on the PCI bus. The SYM53C1010 SCSI function asserts the Bus Request (PCIREQ/) output when the DMA FIFO can accommodate a transfer of at least one burst threshold of ...
Page 187
... Command. If this bit is set, then the destination address is in I/O space; if cleared, the destination address is in memory space. This function is useful for memory-to-register operations using the Memory Move instruction when a SYM53C1010 SCSI function is I/O mapped. Bits 4 and 5 SCSI Registers Number of 64-bit BL1 ...
Page 188
... Multiple command is used on all read cycles when it is legal. Burst Opcode Fetch Enable Setting this bit causes the SYM53C1010 SCSI function to fetch instructions in burst mode. Specifically, the chip bursts in the first two Dwords of all instructions using a single bus ownership. If the instruction is a Memory-to- Memory Move type, the third Dword is accessed in a subsequent bus ownership ...
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Register: 0x39 DMA Interrupt Enable (DIEN) Read/Write MDPE This register contains the interrupt mask bits corresponding to the interrupting conditions described in the interrupt is masked by clearing the appropriate mask bit. ...
Page 190
... The prefetch unit, when enabled, fetches 8 Dwords of instructions and instruction operands in bursts Dwords. Prefetching instructions allows the SYM53C1010 SCSI function to make more efficient use of the system PCI bus, thus improving overall system performance. A flush occurs whenever the PFF bit is set, ...
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... PCI bus. Prefetches of SCRIPTS instructions are 32-bits in width. SSM Single-Step Mode Setting this bit causes the SYM53C1010 SCSI function to stop after executing each SCRIPTS instruction and to generate a single step interrupt. When this bit is cleared the SYM53C1010 SCSI function does not stop after each instruction ...
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... R COM 4-70 Registers DMA SCRIPTS Pointer (DSP) set. This bit is required if the SYM53C1010 SCSI function is in one of the following modes: Manual start mode – Bit 0 in the (DMODE) register is set Single-step mode – Bit 4 in the register is set When the SYM53C1010 SCSI function is executing ...
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Registers: 0x3C–0x3F Adder Sum Output (ADDER) Read Only ADDER Register: 0x40 SCSI Interrupt Enable Zero (SIEN0) Read/Write 7 M/A 0 This register contains the interrupt mask bits corresponding to ...
Page 194
... Enable Response to Selection bit in the SCSI Chip ID (SCID) register. Reselected When set, this bit indicates the SYM53C1010 SCSI function is reselected by a SCSI target device. For this to occur, set the Enable Response to Reselection bit in the SCSI Chip ID (SCID) register. ...
Page 195
... Chip Test Four (CTEST4) UDC Unexpected Disconnect This condition only occurs in the initiator mode. It happens when the target, which the SYM53C1010 SCSI function is connected to, unexpectedly disconnects from the SCSI bus. See the SCSI Disconnect Unexpected bit in the SCSI Control Two (SCNTL2) information on expected versus unexpected disconnects ...
Page 196
... Registers Reserved SCSI Bus Mode Change Setting this bit allows the SYM53C1010 to generate an interrupt when the DIFFSENS pin detects a change in voltage level that indicates the SCSI bus has changed between SE, LVD, or HVD modes. For example, when this bit is cleared and the SCSI bus changes modes, IRQ/ ...
Page 197
... Reading this register clears any bits that are set at the time the register is read, but does not necessarily clear the register because additional interrupts may be pending; the SYM53C1010 SCSI functions stack interrupts. SCSI interrupt conditions are individually masked through the SCSI Interrupt Enable Zero (SIEN0) ...
Page 198
... SEL RSL SGE 4-76 Registers Selected This bit is set when the SYM53C1010 SCSI function is selected by another SCSI device. For the SYM53C1010 SCSI function to respond to selection attempts, the Enable Response to Selection bit must be set in the Chip ID (SCID) register. The (RESPID0) and Response ID One (RESPID1) must hold the chip’ ...
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... A SCRIPTS RAM parity error occurs. UDC Unexpected Disconnect This bit is set when the SYM53C1010 SCSI function is operating in the initiator mode and the target device unexpectedly disconnects from the SCSI bus. This bit is only valid when the SYM53C1010 SCSI function operates in the initiator mode. When the SCSI function operates in the low level mode, any disconnect causes an interrupt, even a valid SCSI disconnect ...
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... SE, LVD, or HVD modes. Reserved Selection or Reselection Time-Out This bit is set when the SCSI device which the SYM53C1010 SCSI function is attempting to select or reselect does not respond within the programmed time-out period. See the description of the Zero (STIME0) register, bits [3:0], for more information on the time-out timer ...