AT32UC3A0256AU Atmel Corporation, AT32UC3A0256AU Datasheet - Page 80
AT32UC3A0256AU
Manufacturer Part Number
AT32UC3A0256AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0256AU
Flash (kbytes)
256 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A0128 PDF datasheet #4
- AT32UC3A0128 PDF datasheet #5
- AT32UC3A0128AU PDF datasheet #6
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- Download datasheet (11Mb)
32058K AVR32-01/12
13.6.10
Name:
Access Type:
•
•
•
•
•
•
•
•
POR Power-on Reset
BOD: Brown-out Reset
EXT: External Reset Pin
WDT: Watchdog Reset
JTAG: JTAG reset
CPUERR: CPU Error
OCDRST: OCD Reset
JTAGHARD: JTAG Hard Reset
CPUERR
31
23
15
7
-
-
-
The CPU was reset due to the supply voltage being lower than the power-on threshold level.
The CPU was reset due to the supply voltage being lower than the brown-out threshold level.
The CPU was reset due to the RESET pin being asserted.
The CPU was reset because of a watchdog timeout.
The CPU was reset by setting the bit RC_CPU in the JTAG reset register.
The CPU was reset because it had detected an illegal access.
The CPU was reset because the RES strobe in the OCD Development Control register has been written to one.
The chip was reset by setting the bit RC_OCD in the JTAG reset register or by using the JTAG HALT instruction.
Reset Cause
30
22
14
RCAUSE
Read-only
6
-
-
-
-
29
21
13
5
-
-
-
-
JTAG
28
20
12
4
-
-
-
WDT
27
19
11
3
-
-
-
EXT
26
18
10
2
-
-
-
JTAGHARD
BOD
25
17
9
1
-
-
AT32UC3A
OCDRST
POR
24
16
8
0
-
-
80
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