AT32UC3B0128 Atmel Corporation, AT32UC3B0128 Datasheet - Page 316
AT32UC3B0128
Manufacturer Part Number
AT32UC3B0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0128
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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21.6.4.15
Figure 21-27. Receiver Behavior when Operating with Hardware Handshaking
Figure 21-28. Transmitter Behavior when Operating with Hardware Handshaking
32059L–AVR32–01/2012
RXBUFF
Write
RXD
RTS
CR
RXEN = 1
Hardware Handshaking
bit (CSR.RXBRK) is set. Writing a one to CR.RSTSTA will clear CSR.RXBRK. An end of break
will also set CSR.RXBRK, and is assumed when TX is high for at least 2/16 of a bit period in
asynchronous mode, or when a high level is sampled in synchronous mode.
The USART features an out-of-band hardware handshaking flow control mechanism, imple-
mentable by connecting the RTS and CTS pins with the remote device, as shown in
26.
Figure 21-26. Connection with a Remote Device for Hardware Handshaking
Writing 0x2 to the MR.MODE field configures the USART to operate in this mode. The receiver
will drive its RTS pin high when disabled or when the Reception Buffer Full bit (CSR.RXBUFF) is
set by the Buffer Full signal from the Peripheral DMA controller. If the receivers RTS pin is high,
the transmitters CTS pin will also be high and only the active character transactions will be com-
pleted. Allocating a new buffer to the DMA controller by clearing RXBUFF, will drive the RTS pin
low, allowing the transmitter to resume transmission. Detected level changes on the CTS pin
can trigger interrupts, and are reported by the CTS Input Change bit in the Channel Status Reg-
ister (CSR.CTSIC).
Figure 21-27
functionality.
CTS
TXD
illustrates receiver functionality, and
USART
TXD
RXD
CTS
RTS
Figure 21-28
RXD
TXD
RTS
CTS
Remote
Device
illustrates transmitter
RXDIS = 1
Figure 21-
316
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