AT32UC3B0128 Atmel Corporation, AT32UC3B0128 Datasheet - Page 39
AT32UC3B0128
Manufacturer Part Number
AT32UC3B0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B0128
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
44
Ext Interrupts
44
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
4
Twi (i2c)
1
Uart
3
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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O s c 1
c lo c k
O s c 0
9.5.4.1
9.5.5
32059L–AVR32–01/2012
c lo c k
P L L O S C
0
1
Synchronous clocks
Enabling the PLL
D iv id e r
P L L D I V
I n p u t
When the PLL is switched on, or when changing the clock source or multiplication factor for the
PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital
logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from
receiving a too high frequency and thus become unstable.
Figure 9-3.
PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1
as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and
division factors, respectively, creating the voltage controlled ocillator frequency f
frequency f
If PLLOPT[1] field is set to 0:
If PLLOPT[1] field is set to 1:
The PLLn:PLLOPT field should be set to proper values according to the PLL operating fre-
quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.
The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen-
erated on a 0 to 1 transition of these bits.
The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the
common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main
clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from
f
f
f
f
VCO
VCO
PLL
PLL
= f
= f
= (PLLMUL+1)/(PLLDIV) • f
= 2*(PLLMUL+1) • f
PLL
D iv id e r
O u t p u t
D e t e c t o r
P L L M U L
VCO.
VCO
P h a s e
PLL with control logic and filters
:
/ 2
.
P L L O P T
V C O
OSC
if PLLDIV = 0.
f
OSC
v c o
if PLLDIV > 0.
D e t e c t o r
1 / 2
L o c k
P L L O P T [ 1 ]
0
1
f
P L L
M a s k
VCO
L o c k b it
and the PLL
P L L c lo c k
39
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