AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 12
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
AT32UC3B1128
Manufacturer Part Number
AT32UC3B1128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B1128
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B1128-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 12 of 377
- Download datasheet (5Mb)
12
SS - Secure State
H - Java Handle
J - Java State
DM - Debug State Mask
D - Debug State
M2, M1, M0 - Execution Mode
AVR32
Figure 2-7.
This bit is indicates if the processor is executing in the secure state. For more details, see chap-
ter 4. The bit is initialized in an IMPLEMENTATION DEFINED way at reset.
This bit is included to support different heap types in the Java Virtual Machine. For more details,
see chapter 3. The bit is cleared at reset.
The processor is in Java state when this bit is set. The incoming instruction stream will be
decoded as a stream of Java bytecodes, not RISC opcodes. The bit is cleared at reset. This bit
should not be modified by the user as undefined behaviour may result.
If this bit is set, the Debug State is masked and cannot be entered. The bit is cleared at reset,
and can both be read and written by software.
The processor is in debug state when this bit is set. The bit is cleared at reset and should only be
modified by debug hardware, the breakpoint instruction or the retd instruction. Undefined behav-
iour may result if the user tries to modify this bit manually.
These bits show the active execution mode. The settings for the different modes are shown in
Table 2-5 on page
supervisor mode after reset. These bits are modified by hardware, or execution of certain
instructions like scall, rets and rete. Undefined behaviour may result if the user tries to modify
these bits manually.
B i t 1 5
R
0
T
0
0
-
The Status Register low halfword
0
-
13. M2 and M1 are cleared by reset while M0 is set so that the processor is in
0
-
0
-
0
-
0
-
0
-
0
-
L
0
Q
0
V
0
N
0
Z
0
B i t 0
C
0
B it n a m e
In itia l v a lu e
C a r r y
Z e r o
S ig n
O v e r f lo w
S a tu r a tio n
L o c k
R e s e r v e d
S c r a tc h
R e g is te r R e m a p E n a b le
32000D–04/2011
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