AT32UC3B1128 Atmel Corporation, AT32UC3B1128 Datasheet - Page 134
AT32UC3B1128
Manufacturer Part Number
AT32UC3B1128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3B0128.pdf
(684 pages)
5.AT32UC3B0128.pdf
(107 pages)
Specifications of AT32UC3B1128
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
60 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
28
Ext Interrupts
28
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
6
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT32UC3B1128-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3B0128 PDF datasheet #4
- AT32UC3B0128 PDF datasheet #5
- Current page: 134 of 377
- Download datasheet (5Mb)
134
AVR32
ANDH, ANDL – Logical AND into high or low half of register
Architecture revision:
Architecture revision1 and higher.
Description
Performs a bitwise logical AND between the high or the low halfword in the specified register and
a constant. The result is stored in the high or the low halfword of the destination register while
the other bits remain unchanged. The Clear Other Half (COH) parameter allows the other half to
be cleared.
Operation:
I.
II.
III.
IV.
Syntax:
I.
II.
III.
IV.
Operands:
I, II, III, IV.
Status Flags:
Opcode
31
15
1
Rd[31:16] ← Rd[31:16] ∧ imm16;
Rd[31:16] ← Rd[31:16] ∧ imm16;
Rd[15:0] ← 0;
Rd[15:0] ← Rd[15:0] ∧ imm16;
Rd[15:0] ← Rd[15:0] ∧ imm16;
Rd[31:16] ← 0;
andh
andh
andl
andl
d ∈ {0, 1, …, 15}
imm ∈ {0, 1, ..., 65535}
Q:
V:
N:
Z:
C:
Format I, II:
1
29
1
Rd, imm
Rd, imm, COH
Rd, imm
Rd, imm, COH
Not affected
Not affected
N ← RES[31]
Z ← (RES[31:0] == 0)
Not affected
28
0
0
26
1
COH
25
24
0
imm16
0
0
0
20
1
19
Rd
32000D–04/2011
0
16
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