AT32UC3C264C Atmel Corporation, AT32UC3C264C Datasheet - Page 39
AT32UC3C264C
Manufacturer Part Number
AT32UC3C264C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C264C
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C264C-A2UR
Manufacturer:
INTERSIL
Quantity:
1 670
Part Number:
AT32UC3C264C-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
5. Memories
5.1
32117CS–AVR-08/11
Embedded Memories
•
•
•
Internal High-Speed Flash (See
Internal High-Speed SRAM, Single-cycle access at full speed (See
Supplementary Internal High-Speed System SRAM (HSB RAM), Single-cycle access at full speed
– 512 Kbytes
– 256 Kbytes
– 128 Kbytes
– 64 Kbytes
– 64 Kbytes
– 32 Kbytes
– 16 Kbytes
– Memory space available on System Bus for peripherals data.
– 4 Kbytes
• 0 Wait State Access at up to 33 MHz in Worst Case Conditions
• 1 Wait State Access at up to 66 MHz in Worst Case Conditions
• Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding
• Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation
• 100 000 Write Cycles, 15-year Data Retention Capability
• Sector Lock Capabilities, Bootloader Protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User Page For Data To Be Preserved During Chip Erase
penalty of 1 wait state access
to only 15% compared to 0 wait state operation
Table 5-1 on page
40)
Table 5-1 on page
AT32UC3C
40)
39