AT32UC3C264C Atmel Corporation, AT32UC3C264C Datasheet - Page 70
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AT32UC3C264C
Manufacturer Part Number
AT32UC3C264C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C264C
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
45
Ext Interrupts
64
Usb Transceiver
1
Quadrature Decoder Channels
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
5
Twi (i2c)
2
Uart
4
Can
2
Lin
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
3
Output Compare Channels
13
Input Capture Channels
6
Pwm Channels
14
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C264C-A2UR
Manufacturer:
INTERSIL
Quantity:
1 670
Part Number:
AT32UC3C264C-U
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
7.9
7.9.1
Table 7-44.
32117CS–AVR-08/11
Parameter
Startup time from power-up, using
regulator
Startup time from reset release
Wake-up
Timing Characteristics
Startup, Reset, and Wake-up Timing
Maximum Reset and Wake-up Timing
Idle
Frozen
Standby
Stop
Deepstop
Static
The startup, reset, and wake-up timings are calculated using the following formula:
Where
clock the startup time of the oscillator,
stop, deepstop, and static sleep modes. Please refer to the source for the CPU clock in the
”Oscillator Characteristics” on page 57
t
t
CPU
=
t
CONST
is the period of the CPU clock. If another clock source than RCSYS is selected as CPU
t
CONST
VDDIN_5 rising (10 mV/ms)
Time from V
the decode stage of CPU. VDDCORE is supplied by
the internal regulator.
Time from releasing a reset source (except POR,
BOD18, and BOD33) to the first instruction entering
the decode stage of CPU.
From wake-up event to the first instruction entering
the decode stage of the CPU.
Measuring
+
N
and
CPU
×
N
CPU
VDDIN_5
t
CPU
are found in
=0 to the first instruction entering
for more details about oscillator startup times.
t
OSCSTART
Table
7-44.
, must be added to the wake-up time in the
t
CONST
Max
268+
268+
268+
is the delay relative to RCSYS,
t
CONST
t
t
t
2600
1240
OSCSTART
OSCSTART
OSCSTART
268
268
0
(in µs)
AT32UC3C
Max
209
209
212
212
212
N
19
0
0
CPU
70