AT32UC3L064 Atmel Corporation, AT32UC3L064 Datasheet - Page 187
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AT32UC3L064
Manufacturer Part Number
AT32UC3L064
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L016.pdf
(843 pages)
4.AT32UC3L016.pdf
(110 pages)
Specifications of AT32UC3L064
Flash (kbytes)
64 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3L016 PDF datasheet #3
- AT32UC3L016 PDF datasheet #4
- Current page: 187 of 843
- Download datasheet (13Mb)
13.5.2
13.5.3
32099G–06/2011
32KHz Oscillator (OSC32K) Operation
Digital Frequency Locked Loop (DFLL) Operation
The SCIF masks the oscillator outputs during the start-up time, to ensure that no unstable clocks
propagate to the digital logic.
The OSCn Ready bit (OSCnRDY) in the Power and Clock Status Register (PCLKSR) is set
when the oscillator is stable and ready to be used as clock source. An interrupt can be gener-
ated on a zero-to-one transition on OSCnRDY.
Rev: 1.0.1.1
The 32KHz oscillator operates as described for the oscillator above. The 32KHz oscillator can
be used as source clock for the Asynchronous Timer (AST) and the Watchdog Timer (WDT).
The 32KHz oscillator can be used as source for the generic clocks.
The oscillator is disabled by default after reset. When the oscillator is disabled, the XIN32 and
XOUT32 pins can be used as general-purpose I/Os. When the oscillator is configured to use an
external clock, the clock must be applied to the XIN32 pin while the XOUT32 pin can be used as
general-purpose I/O.
The oscillator is enabled writing a one to the OSC32 Enable bit (OSC32EN) bit in the 32 KHz
Oscillator Control Register (OSCCTRL32). The oscillator has to be disabled by writing a zero to
the OSC32EN bit, while keeping the other bits unchanged. Writing to OSC32EN while also writ-
ing to other bits may result in unpredictable behavior. Operation mode (external clock or crystal)
is chosen by writing to the Oscillator Mode (MODE) bit in OSCCTRL32. The oscillator is an ultra-
low-power design and remains enabled in all sleep modes.
The start-up time of the 32KHz oscillator is selected by writing to the Oscillator Start-up Time
field (STARTUP) in the OSCCTRL32 register. The SCIF masks the oscillator output during the
start-up time, to ensure that no unstable clock cycles propagate to the digital logic.
The OSC32 Ready bit (OSC32RDY) in the Power and Clock Status Register (PCLKSR) is set
when the oscillator is stable and ready to be used as clock source. An interrupt can be gener-
ated on a zero-to-one transition on OSC32RDY.
As a crystal oscillator usually requires a very long start-up time (up to 1 second), the 32 KHz
oscillator will keep running across resets, except Power-On-Reset (POR).
The 32KHz oscillator also has a 1KHz output. This is enabled by writing a one to the Enable
1 KHz output bit (EN1K) in OSCCTRL32 register. If the 32KHz output clock is not needed when
1K is enabled, this can be disabled by writing a zero to the Enable 32 KHz output bit (EN32K) in
the OSCCTRL32 register. EN32K is set after a POR.
The 32 KHz oscillator has two possible sets of pins. To select between them write to the Pin
Select bit (PINSEL) in the OSCCTRL32 register. If the 32 KHz oscillator is to be used in Shut-
down mode, PINSEL have to be written to one, and XIN32_2 and XOUT32_2 has to be used.
Rev: 2.0.1.1
The DFLL is controlled by the Digital Frequency Locked Loop Interface (DFLLIF). The DFLL is
disabled by default, but can be enabled to provide a high-frequency source clock for synchro-
nous and generic clocks.
Features:
AT32UC3L016/32/64
187
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