AT80C51RD2 Atmel Corporation, AT80C51RD2 Datasheet - Page 60

• Manufacturer Part Number: AT80C51RD2
• Manufacturer: Atmel Corporation

Specifications of AT80C51RD2

• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Uart: 1
• Sram (kbytes): 1.25
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Watchdog: Yes

16. Power-off Flag
60
AT80C51RD2
The Power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”
reset.
A cold start reset is the one induced by V
applied to the device and could be generated for example by an exit from power-down.
The Power-off flag (POF) is located in PCON register (Table 16-1). POF is set by hardware
when V
ing the user to determine the type of reset.
Table 16-1.
PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit addressable
CC
Number
SMOD1
rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-
Bit
7
7
6
5
4
3
2
1
0
PCON Register
Mnemonic Description
SMOD0
SMOD1
SMOD0
POF
GF1
GF0
IDL
Bit
PD
6
-
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-off Flag
Cleared to recognize next reset type.
Set by hardware when V
software.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
5
-
CC
switch-on. A warm start reset occurs while V
POF
4
CC
rises from 0 to its nominal voltage. Can also be set by
GF1
3
GF0
2
PD
1
4113D–8051–01/09
CC
IDL
0
is still