AT89C51CC03 Atmel Corporation, AT89C51CC03 Datasheet - Page 116

• Manufacturer Part Number: AT89C51CC03
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC03

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 37
• Spi: 1
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 2.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

116
AT89C51CC03
Table 62. CANBT3 Register
CANBT3 (S:B6h)
CAN Bit Timing Registers 3
Note:
No default value after reset.
Number
Bit
6-4
3-1
7
-
7
0
The CAN controller bit timing registers must be accessed only if the CAN controller is dis-
abled with the ENA bit of the CANGCON register set to 0.
See Figure 52.
Bit Mnemonic Description
PHS2 2
PHS2 2:0
PHS1 2:0
SMP
6
-
PHS2 1
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Phase Segment 2
This phase is used to compensate for phase edge errors. This segment can
be shortened by the re-synchronization jump width.
Phase segment 2 is the maximum of Phase segment 1 and the Information
Processing Time (= 2TQ).
Phase Segment 1
This phase is used to compensate for phase edge errors. This segment can
be lengthened by the re-synchronization jump width.
Sample Type
0 - once, at the sample point.
1 - three times, the threefold sampling of the bus is the sample point and twice
over a distance of a 1/2 period of the Tscl. The result corresponds to the
majority decision of the three values.
5
PHS2 0
4
Tphs2 = Tscl x (PHS2[2..0] + 1)
Tphs1 = Tscl x (PHS1[2..0] + 1)
PHS1 2
3
PHS1 1
2
4182O–CAN–09/08
PHS1 0
1
SMP
0