AT89C51CC03 Atmel Corporation, AT89C51CC03 Datasheet - Page 46
AT89C51CC03
Manufacturer Part Number
AT89C51CC03
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C51CC03.pdf
(7 pages)
2.AT89C51CC03.pdf
(198 pages)
3.AT89C51CC03.pdf
(32 pages)
4.AT89C51CC03.pdf
(27 pages)
Specifications of AT89C51CC03
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
40 MHz
Cpu
8051-12C
Max I/o Pins
37
Spi
1
Uart
1
Can
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
2.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART/CAN
Watchdog
Yes
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Overview of FM0
Operations
Flash Registers (SFR)
FCON Register
46
AT89C51CC03
The CPU interfaces to the flash memory through the FCON register, AUXR1 register
and FSTA register.
These registers are used to map the column latches, HSB, extra row and EEDATA in
the working data or code space.
Table 13. FCON Register
FCON Register (S:D1h)
Flash Control Register
Reset Value= 0000 0000b
Number
FPL3
Bit
7-4
2-1
7
3
0
Mnemonic Description
FMOD1:0
FBUSY
FPL3:0
FPL2
FPS
Bit
6
Programming Launch Command Bits
Write 5Xh followed by AXh to launch the programming according to FMOD1:0.
(see Table 16.)
Flash Map Program Space
When this bit is set:
The MOVX @DPTR, A instruction writes in the columns latches space
When this bit is cleared:
The MOVX @DPTR, A instruction writes in the regular XDATA memory space
Flash Mode
See Table 16.
Flash Busy
Set by hardware when programming is in progress.
Clear by hardware when programming is done.
Can not be changed by software.
FPL1
5
FPL0
4
FPS
3
FMOD1
2
4182O–CAN–09/08
FMOD0
1
FBUSY
0