AT89C51CC03 Atmel Corporation, AT89C51CC03 Datasheet - Page 2

• Manufacturer Part Number: AT89C51CC03
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC03

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 37
• Spi: 1
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 2.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

2
Workaround
Workaround implementation
AT89C51CC03/C/U Errata Sheet
If the transmitter lost arbitration against another node, two conditions can occur :
1. At least one Receive MOB of the chip are programmed to accept the incoming
2. No Receive MOB of the chip are programmed to accept the incoming message.
Always have a Receive MOB enabled ready to accept any incoming messages. Thanks
to the implementation of the CAN interface, a Receive MOB must be enable at latest,
before the 1
message OK) immediately after the 6th bit of the End of Frame field. This will leave in
CAN2.0A mode a minimum 19-bit time delay to respond to the end of message interrupt
(RXOK) and re-enable the Receive MOB before the start of the DLC field of the next
incoming message. This minimum delay will be 39-bit time in CAN2.0B. See CAN2.0A
CAN2.0B frame timings below.
The workaround is to have the last MOb (MOb14) as "spy" enabled all the time; it is the
MOb of lowest priority : If a Mob other than MOb14 is programmed in receive mode and
its acceptance filter matches with the incoming message ID, this Mob will take the mes-
sage. MOb14 will only take messages than no other MObs will have accepted. MOb14
will need to be re-enabled fast enough to manage back to back frames. The deadline to
do this is the beginning of DLC slot of incoming frames as explained above.
message. In this case, the transmitter will wait for the next 3-bit Intermission to
retry its transmission.
In this case the transmitter will wait for a 4-bit Intermission to retry its transmis-
sion. In this case, any other CAN nodes ready to transmit after a 3-bit
Intermission will start transmit before the chip transmitter, even if their messages
have lower priority IDs.
st
bit of the DLC field. The Receive MOB status register is written (RXOK if
CAN2.0A
CAN2.0B
T 1
T 1
T 1
T 1
T 1
T 1
19 bit time minimum
39 bit time minimum
T 2
T 2
T 2
4293G–CAN–06/05
T 2
T 2
T 2