AT89LP214 Atmel Corporation, AT89LP214 Datasheet - Page 25

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AT89LP214

Manufacturer Part Number
AT89LP214
Description
Manufacturer
Atmel Corporation
Datasheet

Specifications of AT89LP214

Flash (kbytes)
2 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
12
Spi
1
Uart
1
Sram (kbytes)
0.125
Operating Voltage (vcc)
2.4 to 5.0
Timers
2
Isp
SPI/OCD
Watchdog
Yes
13.1.2
13.1.3
3538E–MICRO–11/10
Input-only Mode
Open-drain Output
Figure 13-1. Quasi-bidirectional Output
The input only port configuration is shown in
input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of
P1.3, P3.2 and P3.3 is not disabled during Power-down (see
safely driven to 5.5V even when operating at lower V
the Schmitt trigger will be set by the V
Figure 13-2. Input Only
Figure 13-3. Input Only for P1.3, P3.2 and P3.3
The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor
of the port pin when the port latch contains a logic “0”. To be used as a logic output, a port con-
figured in this manner must have an external pull-up, typically a resistor tied to V
down for this mode is the same as for the quasi-bidirectional mode. The open-drain port configu-
ration is shown in
Power-down (see
operating at lower V
the V
CC
Register
From Port
level and must be taken into consideration.
Input
Input
Data
Data
Figure
Figure
CC
PWD
levels; however, the input threshold of the Schmitt trigger will be set by
13-4.The input circuitry of P1.3, P3.2 and P3.3 is not disabled during
13-3). Open-drain pins can be safely pulled high to 5.5V even when
1 Clock Delay
(D Flip-Flop)
CC
level and must be taken into consideration.
Figure
Input
Data
PWD
13-2. The output drivers are tristated. The
CC
V
Strong
levels; however, the input threshold of
CC
Port
Pin
Port
Pin
Figure
AT89LP213/214
V
Weak
Very
CC
13-3). Input pins can be
V
Weak
CC
CC
Port
Pin
. The pull-
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