AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 205

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17.2
17.3
7734P–AVR–08/10
Operation
Starting a Conversion
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation.
The minimum value represents GND and the maximum value represents the voltage on the AREF pin
minus 1 LSB. Optionally, AV
by writing to the REFSn bits in the ADMUX Register. The internal voltage reference may thus be decou-
pled by an external capacitor at the AREF pin to improve noise immunity.
The analog input channel are selected by writing to the MUX bits in ADMUX. Any of the ADC input
pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the
ADC.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference is set by the
REFS1 and REFS0 bits in ADMUX register, whatever the ADC is enabled or not. The ADC does not con-
sume power when ADEN is cleared, so it is recommended to switch off the ADC before entering power
saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and ADCL. By
default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the
ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read ADCH.
Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data Registers belongs
to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if
ADCL has been read, and a conversion completed before ADCH is read, neither register is updated and
the result from the conversion is lost. When ADCH is read, ADC access to the ADCH and ADCL Regis-
ters is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. The ADC access to
the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt will trigger even if
the result is lost.
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit
stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is
completed. If a different data channel is selected while a conversion is in progress, the ADC will finish the
current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is enabled
by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is selected by set-
ting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS bits for a list of the
trigger sources). When a positive edge occurs on the selected trigger signal, the ADC prescaler is reset and
a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger sig-
nal is still set when the conversion completes, a new conversion will not be started. If another positive
edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an interrupt flag
will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared.
A conversion can thus be triggered without causing an interrupt. However, the interrupt flag must be
cleared in order to trigger a new conversion at the next interrupt event.
Triggering from the PSC’s synchronization signal is different as there is no flag. In this case, a new con-
version is started at each triggering signal. However, a single shot mode can be activated by setting the bit
ADSSEN in ADCSRB register. In this case the synchronization signal is blocked until the ADCH registed
is read.
CC
or an internal 2.56V reference voltage may be connected to the AREF pin
AT90PWM81
205