AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 94

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

11.6.2
11.7
94
Timer/Counter Timing Diagrams
AT90PWM81
Clear Timer on Compare Match (CTC) Mode
not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV1
Flag, the timer resolution can be increased by software. There are no special cases to consider in the Nor-
mal mode, a new counter value can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum interval
between the external events must not exceed the resolution of the counter. If the interval between events
are too long, the timer overflow interrupt must be used to extend the resolution for the capture unit.
In Clear Timer on Compare or CTC mode (WGM13 = 1, previous mode 12), the ICR1 Register are used
to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value
(TCNT1) matches the ICR1 . The ICR1 define the top value for the counter, hence also its resolution. This
mode allows greater control of the compare match output frequency. It also simplifies the operation of
counting external events.
The timing diagram for the CTC mode is shown in
until a compare match occurs with ICR1, and then counter (TCNT1) is cleared.
Figure 11-5.
An interrupt can be generated at each time the counter value reaches the TOP value by using the ICF1
Flag . If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
However, changing the TOP to a value close to BOTTOM when the counter is running with none or a low
prescaler value must be done with care since the CTC mode does not have the double buffering feature. If
the new value written to ICR1 is lower than the current value of TCNT1, the counter will miss the com-
pare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting
at 0x0000 before the compare match can occur. In many cases this feature is not desirable.
As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the counter
counts from MAX to 0x0000.
The Timer/Counter is a synchronous design and the timer clock (clk
enable signal in the following figures. The figures include information on when Interrupt Flags are set.
Figure 11-6
TCNTn
shows the count sequence close to TOP in various modes.
CTC Mode, Timing Diagram
Figure
11-5. The counter value (TCNT1) increases
T1
) is therefore shown as a clock
(Interrupt on TOP)
ICFn Interrupt Flag Set
7734P–AVR–08/10