AT90PWM2B Atmel Corporation, AT90PWM2B Datasheet - Page 212
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AT90PWM2B
Manufacturer Part Number
AT90PWM2B
Description
Manufacturer
Atmel Corporation
Specifications of AT90PWM2B
Flash (kbytes)
8 Kbytes
Pin Count
24
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
19
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
2
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
1
Pwm Channels
7
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM2B-16SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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19.3.2
19.3.3
212
AT90PWM2/3/2B/3B
Parity Bit Calculation
Manchester encoding
The frame format used by the EUSART can be configured through the following
USART/EUSART registers:
•
•
USBS (UCSRC register of USART) and EUSBS (EUCSRB register of EUSART) select the num-
ber of stop bits to be processed respectively by the transmiter and the receiver. The receiver
stores the two stop bit values when configured in Manchester mode. When configured in level
encoded mode, the second stop bit is ignored (behavior similar as the USART).
The parity bit behavior is similar to the USART mode, except for the Manchester encoded mode,
where no parity bit can be inserted or detected (should be configured to none with the UPM1:0
bits. The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used,
the result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows:
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
Manchester encoding (also know as Biphase Code) is a synchronous clock encoding technique
used to encode the clock and data of a synchronous bit stream. In this technique, the actual
binary data to be transmitted are not sent as a sequence of logic 1's and 0's as in level encoded
way as in standard USART (known technically as Non Return to Zero (NRZ)). Instead, the bits
are translated into a slightly different format that has a number of advantages over using straight
binary encoding (i.e. NRZ).
Manchester encoding follows the rules:
•
•
Figure 19-2. Manchester Bi-phase levels
P
P
d
n
even
odd
UTxS3:0 and URxS3:0 (EUCSRA of EUSART register) select the number of data bits per
frame
UPM1:0 bits enable and set the type of parity bit (when configured in Manchester mode, the
parity should be fixed to none).
If the original data is a Logic 1, the Manchester code is: 0 to 1 (upward transition at bit
center)
If the original data is a Logic 0, the Manchester code is: 1 to 0 (downward transition at bit
center)
Parity bit using even parity
Parity bit using odd parity
Data bit n of the character
P
P
even
odd
Logical 0
=
=
d
d
n 1
n 1
–
–
⊕
⊕
…
…
⊕
⊕
d
d
3
3
⊕
⊕
d
d
2
2
Logical 1
⊕
⊕
d
d
1
1
⊕
⊕
d
d
0
0
⊕
⊕
0
1
4317J–AVR–08/10
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