ATmega1281 Atmel Corporation, ATmega1281 Datasheet - Page 174

• Manufacturer Part Number: ATmega1281
• Manufacturer: Atmel Corporation

Specifications of ATmega1281

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 2
• Pwm Channels: 8
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

20. 8-bit Timer/Counter2 with PWM and Asynchronous Operation
20.1
2549N–AVR–05/11
Overview
Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main
features are:
•
•
•
•
•
•
•
A simplified block diagram of the 8-bit Timer/Counter is shown in
placement of I/O pins, see
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the
The Power Reduction Timer/Counter2 bit, PRTIM2, in
page 56
Figure 20-1. 8-bit Timer/Counter Block Diagram
Single Channel Counter
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Frequency Generator
10-bit Clock Prescaler
Overflow and Compare Match Interrupt Sources (TOV2, OCF2A and OCF2B)
Allows Clocking from External 32kHz Watch Crystal Independent of the I/O Clock
Status flags
must be written to zero to enable Timer/Counter2 module.
Timer/Counter
TCCRnA
OCRnA
TCNTn
“Register Description” on page
OCRnB
=
=
Direction
“Pin Configurations” on page
Count
Clear
ASSRn
Synchronized Status flags
ATmega640/1280/1281/2560/2561
Control Logic
TOP
=
TCCRnB
asynchronous mode
Value
BOTTOM
Fixed
TOP
select (ASn)
clk
=
Tn
0
187.
Prescaler
Synchronization Unit
“PRR0 – Power Reduction Register 0” on
2. CPU accessible I/O Registers, includ-
OCnA
(Int.Req.)
OCnB
(Int.Req.)
Generation
Generation
Waveform
Waveform
Figure 17-12.
TOVn
(Int.Req.)
OCnA
OCnB
Oscillator
T/C
clk
For the actual
I/O
clk
clk
I/O
ASY
TOSC1
TOSC2
174