ATmega1281 Atmel Corporation, ATmega1281 Datasheet - Page 195

• Manufacturer Part Number: ATmega1281
• Manufacturer: Atmel Corporation

Specifications of ATmega1281

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 3
• Twi (i2c): 1
• Uart: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 16
• Input Capture Channels: 2
• Pwm Channels: 8
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21. SPI – Serial Peripheral Interface
2549N–AVR–05/11
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega640/1280/1281/2560/2561 and peripheral devices or between several AVR devices.
The ATmega640/1280/1281/2560/2561 SPI includes the following features:
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USART can also be used in Master SPI mode, see
The Power Reduction SPI bit, PRSPI, in
page 50 must be written to zero to enable SPI module.
Figure 21-1. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in
196. The system consists of two shift Registers, and a Master clock generator. The SPI Master
initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
1. Refer to
/2/4/8/16/32/64/128
DIVIDER
Figure 1-1 on page
ATmega640/1280/1281/2560/2561
(1)
2, and
“PRR0 – Power Reduction Register 0” on page 56
Table 13-6 on page 79
“USART in SPI Mode” on page
for SPI pin placement.
Figure 21-2 on page
232.
195
on