ATmega1281 Atmel Corporation, ATmega1281 Datasheet - Page 220
ATmega1281
Manufacturer Part Number
ATmega1281
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1281
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
16
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega1281-8MC
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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22.7.3
2549N–AVR–05/11
Asynchronous Operational Range
Figure 22-7. Stop Bit Sampling and Next Start Bit Sampling
The same majority voting is done to the stop bit as done for the other bits in the frame. If the stop
bit is registered to have a logic 0 value, the Frame Error (FEn) Flag will be set.
A new high to low transition indicating the start bit of a new frame can come right after the last of
the bits used for majority voting. For Normal Speed mode, the first low level sample can be at
point marked (A) in
(B). (C) marks a stop bit of full length. The early start bit detection influences the operational
range of the Receiver.
The operational range of the Receiver is dependent on the mismatch between the received bit
rate and the internally generated baud rate. If the Transmitter is sending frames at too fast or too
slow bit rates, or the internally generated baud rate of the Receiver does not have a similar (see
Table 22-2 on page
frames to the start bit.
The following equations can be used to calculate the ratio of the incoming data rate and internal
receiver baud rate.
D
S
S
S
R
F
M
slow
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
R
slow
mode.
for Double Speed mode.
S
receiver baud rate. R
accepted in relation to the receiver baud rate.
Sum of character size and parity size (D = 5 to 10 bit).
Samples per bit. S = 16 for Normal Speed mode and S = 8 for Double Speed
First sample number used for majority voting. S
Middle sample number used for majority voting. S
is the ratio of the slowest incoming data rate that can be accepted in relation to the
=
M
= 5 for Double Speed mode.
------------------------------------------ -
S 1
–
Figure
221) base frequency, the Receiver will not be able to synchronize the
(
D
+
1
1
+
D S ⋅
1
2
22-7. For Double Speed mode the first low level must be delayed to
)S
+
3
2
S
ATmega640/1280/1281/2560/2561
F
4
fast
5
3
is the ratio of the fastest incoming data rate that can be
6
7
4
8
STOP 1
9
5
10
R
fast
(A)
0/1
6
=
0/1
F
-----------------------------------
(
= 8 for normal speed and S
D
(B)
0/1
0/1
(
+
D
M
1
+
= 9 for normal speed and
)S
2
)S
+
S
M
(C)
F
220
= 4
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