ATmega1284P Atmel Corporation, ATmega1284P Datasheet - Page 23
ATmega1284P
Manufacturer Part Number
ATmega1284P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1284P
Flash (kbytes)
128 Kbytes
Pin Count
44
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
32
Ext Interrupts
32
Usb Speed
No
Usb Interface
No
Spi
3
Twi (i2c)
1
Uart
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Eeprom (bytes)
4096
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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8.5
8272C–AVR–06/11
I/O Memory
The I/O space definition of the ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is
shown in
All ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P I/Os and peripherals are placed
in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD
instructions, transferring data between the 32 general purpose working registers and the I/O
space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the
SBI and CBI instructions. In these registers, the value of single bits can be checked by using the
SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the
I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When
addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to
these addresses. The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P is a com-
plex microcontroller with more peripheral units than can be supported within the 64 location
reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 -
0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore
be used on registers containing such Status Flags. The CBI and SBI instructions work with reg-
isters 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P contains three General Pur-
pose I/O Registers, see
storing any information, and they are particularly useful for storing global variables and Status
Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-
accessible using the SBI, CBI, SBIS, and SBIC instructions.
”Register Summary” on page
ATmega164A/PA/324A/PA/644A/PA/1284/P
”Register Description” on page
553.
24. These registers can be used for
23
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