ATmega169P Atmel Corporation, ATmega169P Datasheet - Page 165
ATmega169P
Manufacturer Part Number
ATmega169P
Description
Manufacturer
Atmel Corporation
Specifications of ATmega169P
Flash (kbytes)
16 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Segment Lcd
100
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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18.5
18.5.1
8018P–AVR–08/10
Register Description
SPCR – SPI Control Register
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Mas-
ter mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to
CPOL functionality is summarized below:
Table 18-3.
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to
example. The CPOL functionality is summarized below:
Table 18-4.
Bit
0x2C (0x4C)
Read/Write
Initial Value
CPOL
CPHA
CPOL Functionality
CPHA Functionality
0
1
0
1
SPIE
R/W
7
0
Figure 18-3 on page 164
SPE
R/W
6
0
DORD
R/W
Figure 18-3 on page 164
5
0
Leading Edge
Leading Edge
MSTR
Sample
Falling
Rising
R/W
Setup
4
0
and
Figure 18-4 on page 164
CPOL
R/W
3
0
and
CPHA
R/W
2
0
Figure 18-4 on page 164
SPR1
ATmega169P
R/W
1
0
Trailing Edge
Trailing Edge
Sample
for an example. The
Falling
Rising
Setup
SPR0
R/W
0
0
SPCR
for an
165