ATmega3290 Atmel Corporation, ATmega3290 Datasheet - Page 241

• Manufacturer Part Number: ATmega3290
• Manufacturer: Atmel Corporation

Specifications of ATmega3290

• Flash (kbytes): 32 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 69
• Ext Interrupts: 32
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 160
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.4.3
2552K–AVR–04/11
LCDFRR – LCD Frame Rate Register
Table 23-3.
Note:
• Bit 7 – Reserved Bit
This bit is reserved bit in the ATmega329/3290/649/6490 and will always read as zero.
• Bits 6:4 – LCDPS2:0: LCD Prescaler Select
The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further
divided by setting the clock divide bits (LCDCD2:0). The different selections are shown in
23-4. Together they determine the prescaled LCD clock (clk
module.
Table 23-4.
• Bit 3 – Reserved Bit
This bit is reserved bit in the ATmega329/3290/649/6490 and will always read as zero.
• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0
The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are
shown in
Bit
(0xE6)
Read/Write
Initial Value
LCDPM3
LCDPS2
1
1
1
0
0
0
0
1
1
1
1
1. LCDPM3 is reserved and will always read as zero in ATmega329/649.
Table
LCDPM2
LCDPS1
LCD Port Mask (Values in bold are only available in ATmega3290/6490)
LCD Prescaler Select
R
23-5. This Clock Divider gives extra flexibility in frame rate selection.
1
1
1
7
–
0
0
0
1
1
0
0
1
1
LCDPS2
R/W
LCDPM1
LCDPS0
6
0
0
1
1
0
1
0
1
0
1
0
1
LCDPS1
R/W
5
0
LCDPM0
Output from
clk
clk
clk
clk
clk
clk
Prescaler
clk
clk
clk
1
0
1
LCD
LCD
LCD
LCDPS0
LCD
LCD
LCD
LCD
LCD
R/W
LCD
4
0
/1024
/2048
/4096
/128
/256
/512
/16
/64
/N
ATmega329/3290/649/6490
I/O Port in Use as
Segment Driver
R
3
–
0
Duty = 1/4, and Frame Rate = 64 Hz
SEG0:36
SEG0:38
SEG0:39
Frequency when LCDCD2:0 = 0,
Applied Prescaled LCD Clock
LCDCD2
R/W
2
0
LCD_PS
LCDCD1
130kHz
260kHz
520kHz
R/W
8.1kHz
33kHz
66kHz
1MHz
2MHz
1
0
), which is clocking the LCD
Maximum Number
of Segments
LCDCD0
R/W
0
0
37
39
40
LCDFRR
Table
241