ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 139
ATmega32M1
Manufacturer Part Number
ATmega32M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32M1
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega32M1-15AD
Manufacturer:
ATMEL
Quantity:
1 448
Part Number:
ATmega32M1-15AD
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATmega32M1-AU
Manufacturer:
TYCO
Quantity:
210
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Figure 17-7. Controlled Start and Stop Mechanism in Centered Mode
Note:
17.6
17.6.1
8209D–AVR–11/10
POCRnRB
POCRnSB
POCRnSA
PSC Counter
Run
PSCOUTnA
PSCOUTnB
See “PCTL – PSC Control Register” on page
Update of Values
Value Update Synchronization
To avoid unasynchronous and incoherent values in a cycle, if an update of one of several values
is necessary, all values are updated at the same time at the end of the cycle by the PSC. The
new set of values is calculated by sofware and the update is initiated by software.
Figure 17-8. Update at the end of complete PSC cycle.
The software can stop the cycle before the end to update the values and restart a new PSC
cycle.
New timing values or PSC output configuration can be written during the PSC cycle. Thanks to
LOCK configuration bit, the new whole set of values can be taken into account after the end of
the PSC cycle.
When LOCK configuration bit is set, there is no update. The update of the PSC internal registers
will be done at the end of the PSC cycle if the LOCK bit is released to zero.
The registers which update is synchronized thanks to LOCK are POC, POM2, POCRnSAH/L,
POCRnRAH/L, POCRnSBH/L and POCRnRBH/L.
See these register’s description starting on
Software
PSC
150.(PCCYC = 1)
Regulation Loop
Calculation
Cycle
With Set i
0
Cycle
With Set i
page
Cycle
With Set i
Writting in
PSC Registers
ATmega16M1/32M1/64M1
148.
Cycle
With Set i
End of Cycle
Request for
an Update
Cycle
With Set j
139
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