ATmega32M1 Atmel Corporation, ATmega32M1 Datasheet - Page 187
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ATmega32M1
Manufacturer Part Number
ATmega32M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32M1
Flash (kbytes)
32 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
ATmega32M1-15AD
Manufacturer:
ATMEL
Quantity:
1 448
Part Number:
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Manufacturer:
ATMEL/爱特梅尔
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Company:
Part Number:
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Manufacturer:
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Quantity:
210
- Current page: 187 of 341
- Download datasheet (6Mb)
19.10.9
8209D–AVR–11/10
CANBT2 – CAN Bit Timing Register 2
• Bit 6:1 – BRP[5:0]: Baud Rate Prescaler
The period of the CAN controller system clock Tscl is programmable and determines the individ-
ual bit timing.
If ‘BRP[5..0]=0’, see
ple Point(s)” on page
• Bit 0 – Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT1 is written.
• Bit 7– Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
• Bit 6:5 – SJW[1:0]: Re-Synchronization Jump Width
To compensate for phase shifts between clock oscillators of different bus controllers, the control-
ler must re-synchronize on any relevant signal edge of the current transmission.
The synchronization jump width defines the maximum number of clock cycles. A bit period may
be shortened or lengthened by a re-synchronization.
• Bit 4 – Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
• Bit 3:1 – PRS[2:0]: Propagation Time Segment
This part of the bit time is used to compensate for the physical delay times within the network. It
is twice the sum of the signal propagation time on the bus line, the input comparator delay and
the output driver delay.
• Bit 0 – Res: Reserved
This bit is reserved for future use. For compatibility with future devices, it must be written to zero
when CANBT2 is written.
Initial Value
Read/Write
Bit
7
-
-
-
Section 19.5.3 “Baud Rate” on page 172
188.
SJW1
R/W
6
0
SJW0
R/W
5
0
Tprs = Tscl × (PRS [2:0] + 1)
Tscl =
Tsjw = Tscl × (SJW [1:0] + 1)
4
-
-
-
ATmega16M1/32M1/64M1
clk
BRP[5:0] + 1
IO
PRS2
R/W
3
0
frequency
PRS1
R/W
and
2
0
Section • “Bit 0 – SMP: Sam-
PRS0
R/W
1
0
0
-
-
-
CANBT2
187
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