ATmega64M1 Automotive Atmel Corporation, ATmega64M1 Automotive Datasheet - Page 131
ATmega64M1 Automotive
Manufacturer Part Number
ATmega64M1 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATMEGA16M1_AUTOMOTIVE.pdf
(25 pages)
3.ATMEGA16M1_AUTOMOTIVE.pdf
(367 pages)
Specifications of ATmega64M1 Automotive
Flash (kbytes)
64 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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Table 13-4.
Note:
7647G–AVR–09/11
Mode
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the
WGMn3
location of these bits are compatible with previous versions of the timer.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Waveform Generation Mode Bit Description
WGMn2
(CTCn)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Table 13-3
correct or the phase and frequency correct, PWM mode.
Table 13-3.
Note:
• Bit 1:0 – WGMn1:0: Waveform Generation Mode
Combined with the WGMn3:2 bits found in the TCCRnB Register, these bits control the count-
ing sequence of the counter, the source for maximum (TOP) counter value, and what type of
waveform generation to be used, see
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes.
PWM” on page
(PWMn1)
WGMn1
COMnA1/COMnB1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1. A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set.
0
0
1
1
(PWMn0) Timer/Counter Mode of Operation
shows the COMnx1:0 bit functionality when the WGMn3:0 bits are set to the phase
See “Phase Correct PWM Mode” on page 123.
WGMn0
Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
107.).
(1)
Normal
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
PWM, Phase Correct, 10-bit
CTC
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
PWM, Phase and Frequency Correct ICRn
PWM, Phase and Frequency Correct OCRnA
PWM, Phase Correct
PWM, Phase Correct
CTC
(Reserved)
Fast PWM
Fast PWM
COMnA0/COMnB0
(1)
0
1
0
1
Atmel ATmega16/32/64/M1/C1
Table
WGM
Description
Normal port operation, OCnA/OCnB disconnected.
WGMn3:0 = 8, 9 10 or 11: Toggle OCnA on Compare
Match, OCnB disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
Clear OCnA/OCnB on Compare Match when
up-counting. Set OCnA/OCnB on Compare Match
when downcounting.
Set OCnA/OCnB on Compare Match when
up-counting. Clear OCnA/OCnB on Compare Match
when downcounting.
13-4. Modes of operation supported by the
n2:0 definitions. However, the functionality and
for more details.
TOP
0xFFFF
0x00FF
0x01FF
0x03FF
OCRnA
0x00FF
0x01FF
0x03FF
ICRn
OCRnA
ICRn
–
ICRn
OCRnA
(See “16-bit Timer/Counter1 with
Update of
OCRn
Immediate
TOP
TOP
TOP
Immediate
TOP
TOP
TOP
BOTTOM
BOTTOM
TOP
TOP
Immediate
–
TOP
TOP
x
at
TOVn Flag
Set on
MAX
MAX
TOP
TOP
TOP
BOTTOM
BOTTOM
BOTTOM
MAX
–
TOP
TOP
BOTTOM
BOTTOM
BOTTOM
BOTTOM
131
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