ATtiny24A Atmel Corporation, ATtiny24A Datasheet - Page 101

• Manufacturer Part Number: ATtiny24A
• Manufacturer: Atmel Corporation

Specifications of ATtiny24A

• Flash (kbytes): 2 Kbytes
• Pin Count: 14
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 12
• Ext Interrupts: 12
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.9
8183D–AVR–04/11
Timer/Counter Timing Diagrams
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM wave-
forms on the OC1x pins. Setting the COM1x[1:0] bits to two will produce a non-inverted PWM
and an inverted PWM output can be generated by setting the COM1x[1:0] to three (See
12-4 on page
for the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or
clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the coun-
ter increments, and clearing (or setting) the OC1x Register at compare match between OCR1x
and TCNT1 when the counter decrements. The PWM frequency for the output when using
phase and frequency correct PWM can be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 12-11 on page 102
TCNTn
OCRnx
OCFnx
(clk
clk
clk
I/O
I/O
Tn
/1)
107). The actual OC1x value will only be visible on the port pin if the data direction
OCRnx - 1
shows the same timing data, but with the prescaler enabled.
f
OCnxPFCPWM
Figure 12-10
OCRnx
OCRnx Value
shows a timing diagram for the setting of OCF1x.
=
--------------------------- -
2 N TOP
⋅
f
clk_I/O
⋅
ATtiny24A/44A/84A
OCRnx + 1
T1
) is therefore shown as a
OCRnx + 2
Table
101