ATtiny261 Atmel Corporation, ATtiny261 Datasheet - Page 11

• Manufacturer Part Number: ATtiny261
• Manufacturer: Atmel Corporation

Specifications of ATtiny261

• Flash (kbytes): 2 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 4
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.12
• Eeprom (bytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

4.5
4.5.1
4.6
2588E–AVR–08/10
Stack Pointer
Instruction Execution Timing
SPH and SPL — Stack Pointer Register
In different addressing modes these address registers function as automatic increment and
automatic decrement (see the instruction set reference for details).
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to
point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack
with the PUSH instruction, and it is decremented by two when the return address is pushed onto
the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is
popped from the Stack with the POP instruction, and it is incremented by two when data is
popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 4-4
vard architecture and the fast access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Y-register
Z-register
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/Write
Initial Value
shows the parallel instruction fetches and instruction executions enabled by the Har-
15
SP15
SP7
7
R/W
R/W
RAMEND
RAMEND
15
7
R29 (0x1D)
15
7
R31 (0x1F)
14
SP14
SP6
6
R/W
R/W
RAMEND
RAMEND
13
SP13
SP5
5
R/W
R/W
RAMEND
RAMEND
CPU
ZH
YH
0
, directly generated from the selected clock source for the
12
SP12
SP4
4
R/W
R/W
RAMEND
RAMEND
RAMEND
11
SP11
SP3
3
R/W
R/W
RAMEND
0
7
R28 (0x1C)
7
R30 (0x1E)
10
SP10
SP2
2
R/W
R/W
RAMEND
RAMEND
9
SP9
SP1
1
R/W
R/W
RAMEND
RAMEND
YL
ZL
0
8
SP8
SP0
0
R/W
R/W
RAMEND
RAMEND
SPH
SPL
11
0
0
0