ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 82

• Manufacturer Part Number: ATtiny43U
• Manufacturer: Atmel Corporation

Specifications of ATtiny43U

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 0.7 to 5.5
• Operating Voltage (vcc): 0.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.5.1
12.5.2
12.5.3
82
ATtiny43U
Force Output Compare
Compare Match Blocking by TCNTn Write
Using the Output Compare Unit
Figure 12-3. Output Compare Unit, Block Diagram
The OCRnx Registers are double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-
ble buffering is disabled. The double buffering synchronizes the update of the OCRnx Compare
Registers to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCRnx Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCRnx Buffer Register, and if double buffering is dis-
abled the CPU will access the OCRnx directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (nx) bit. Forcing Compare Match will not set the
OCFnx Flag or reload/clear the timer, but the OCnx pin will be updated as if a real Compare
Match had occurred (the COMnx1:0 bits settings define whether the OCnx pin is set, cleared or
toggled).
All CPU write operations to the TCNTn Register will block any Compare Match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCRnx to be initial-
ized to the same value as TCNTn without triggering an interrupt when the Timer/Counter clock is
enabled.
Since writing TCNTn in any mode of operation will block all Compare Matches for one timer
clock cycle, there are risks involved when changing TCNTn when using the Output Compare
Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNTn
equals the OCRnx value, the Compare Match will be missed, resulting in incorrect waveform
bottom
FOCn
top
OCRnx
Waveform Generator
WGMn1:0
=
(8-bit Comparator )
DATA BUS
COMnx1:0
TCNTn
OCFnx (Int.Req.)
OCnx
8048B–AVR–03/09