ATtiny44 Automotive Atmel Corporation, ATtiny44 Automotive Datasheet - Page 127
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ATtiny44 Automotive
Manufacturer Part Number
ATtiny44 Automotive
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny44 Automotive
Flash (kbytes)
4 Kbytes
Pin Count
14
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
6
Hardware Qtouch Acquisition
No
Max I/o Pins
12
Ext Interrupts
12
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
256
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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16.3.4
7701E–AVR–02/11
Two-wire Mode
The USI two-wire mode is compliant with the Inter-IC (I2C or TWI) bus protocol, but without
slew rate limiting on outputs and input noise filtering. Pin names used by this mode are SCL
and SDA.
Figure 16-4. Two-wire Mode Operation, Simplified Diagram
Figure 16-4 on page 127
one as slave. Only the physical layer is shown because the system operation is highly depen-
dent of the communication scheme used. The main differences between the master and slave
operation at this level are that the serial clock generation is always done by the master, and
only the slave uses the clock control unit. Clock generation must be implemented in software,
but the shift operation is done automatically by both devices. Note that only clocking on the
negative edge to shift data is practical in this mode. The slave can insert wait states at the start
or end of a transfer by forcing the SCL clock low. This means that the master must always
check if the SCL line was actually released after it has generated a positive edge.
Because the clock also increments the counter, a counter overflow can be used to indicate
that the transfer has completed. The master generates clock by the by toggling the USCK pin
via the PORT register.
The data direction is not given by the physical layer. A protocol, like the one used by the
TWI-bus, must be implemented to control the data flow.
SLAVE
MASTER
Bit7
Bit7
Bit6
Bit6
Bit5
Bit5
Bit4
Bit4
shows two USI units operating in two-wire mode, one as master and
Atmel ATtiny24/44/84 [Preliminary]
Bit3
Bit3
Bit2
Bit2
Bit1
Bit1
Bit0
Bit0
Two-wire Clock
Control Unit
PORTxn
HOLD
SCL
SDA
SCL
SDA
SCL
VCC
127
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