ATtiny87 Automotive Atmel Corporation, ATtiny87 Automotive Datasheet - Page 81
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ATtiny87 Automotive
Manufacturer Part Number
ATtiny87 Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.ATTINY167_AUTOMOTIVE.pdf
(10 pages)
3.ATTINY167_AUTOMOTIVE.pdf
(283 pages)
Specifications of ATtiny87 Automotive
Flash (kbytes)
8 Kbytes
Pin Count
20
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 150
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
3
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT90CAN128_AUTOMOTIVE PDF datasheet
- ATTINY167_AUTOMOTIVE PDF datasheet #2
- ATTINY167_AUTOMOTIVE PDF datasheet #3
- Current page: 81 of 225
- Download datasheet (4Mb)
7701E–AVR–02/11
Figure 13-7. Phase Correct PWM Mode, Timing Diagram
The timer/counter overflow flag (TOV0) is set each time the counter reaches bottom. The inter-
rupt flag can be used to generate an interrupt each time the counter reaches the bottom value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0x1:0 bits to three. Setting the COM0A0
bits to one allows the OC0A pin to toggle on compare matches if the WGM02 bit is set. This
option is not available for the OC0B pin (See
will only be visible on the port pin if the data direction for the port pin is set as output. The
PWM waveform is generated by clearing (or setting) the OC0x register at the compare match
between OCR0x and TCNT0 when the counter increments, and setting (or clearing) the OC0x
register at compare match between OCR0x and TCNT0 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the fol-
lowing equation:
The variable N represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to bottom, the
output will be continuously low, and if set equal to max the output will be continuously high for
non-inverted PWM mode. For inverted PWM, the output will have the opposite logic values.
At the very start of period 2 in
even though there is no compare match. The point of this transition is to guarantee symmetry
around bottom. There are two cases that give a transition without a compare match.
TCNTn
OCn
OCn
Period
Atmel ATtiny24/44/84 [Preliminary]
1
Figure 13-7 on page 81
f
OCnxPCPWM
2
Table 13-4 on page
=
-------------------- -
N
f
clk_I/O
510
OCn has a transition from high to low
3
85). The actual OC0x value
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
(COMnx1:0 = 2)
(COMnx1:0 = 3)
81
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