ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 14
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ATUC128L4U
Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.ATUC128L4U.pdf
(960 pages)
4.ATUC128L4U.pdf
(92 pages)
Specifications of ATUC128L4U
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATUC128L4U-U
Manufacturer:
ATMEL
Quantity:
3 006
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- ATUC128L4U PDF datasheet #3
- ATUC128L4U PDF datasheet #4
- Current page: 14 of 377
- Download datasheet (5Mb)
2.11
14
R - Java register remap
T - Scratch bit
L - Lock flag
Q - Saturation flag
V - Overflow flag
N - Negative flag
Z - Zero flag
C - Carry flag
System registers
AVR32
When this bit is set, the addresses of the registers in the register file is dynamically changed.
This allows efficient use of the register file registers as a stack. For more details, see chapter 3..
The R bit is cleared at reset. Undefined behaviour may result if this bit is modified by the user.
This bit is not set or cleared implicit by any instruction and the programmer can therefore use
this bit as a custom flag to for example signal events in the program. This bit is cleared at reset.
Used by the conditional store instruction. Used to support atomical memory access. Automati-
cally cleared by rete. This bit is cleared after reset.
The saturation flag indicates that a saturating arithmetic operation overflowed. The flag is sticky
and once set it has to be manually cleared by a csrf instruction after the desired action has been
taken. See the Instruction set description for details.
The overflow flag indicates that an arithmetic operation overflowed. See the Instruction set
description for details.
The negative flag is modified by arithmetical and logical operations. See the Instruction set
description for details.
The zero flag indicates a zero result after an arithmetic or logic operation. See the Instruction set
description for details.
The carry flag indicates a carry after an arithmetic or logic operation. See the Instruction set
description for details.
The system registers are placed outside of the virtual memory space, and are only accessible
using the privileged mfsr and mtsr instructions, see
cal locations is IMPLEMENTATION DEFINED, but a maximum of 256 locations can be
addressed with the dedicated instructions. Some of the System Registers are altered automati-
cally by hardware.
The reset value of the System Registers are IMPLEMENTATION DEFINED.
Table 2-7 on page
15. The number of physi-
32000D–04/2011
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