ATUC128L4U Atmel Corporation, ATUC128L4U Datasheet - Page 89

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ATUC128L4U

Manufacturer Part Number
ATUC128L4U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATUC128L4U

Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
1
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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Quantity
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8.3.2.22
8.3.2.23
8.3.2.24
32000D–04/2011
DTLB Read Protection Exception
DTLB Write Protection Exception
Privilege Violation Exception
The DTLB Protection exception is generated when the data memory read violates the access
rights specified by the protection bits of the addressed virtual page.
The DTLB Protection exception is generated when the data memory write violates the access
rights specified by the protection bits of the addressed virtual page.
If the application tries to execute privileged instructions, this exception is issued. The complete
list of priveleged instructions is shown in Table 8-2. When entering the exception routine, the
address of the instruction that caused the exception is stored as yhe stacked return address.
RSR_EX = SR;
RAR_EX = PC;
TLBEAR = FAILING_VIRTUAL_ADDRESS;
TLBEHI[VPN] = FAILING_PAGE_NUMBER;
TLBEHI[I] = 0;
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA + 0x3C;
RSR_EX = SR;
RAR_EX = PC;
TLBEAR = FAILING_VIRTUAL_ADDRESS;
TLBEHI[VPN] = FAILING_PAGE_NUMBER;
TLBEHI[I] = 0;
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA + 0x40;
RSR_EX = SR;
RAR_EX = PC;
SR[R] = 0;
SR[J] = 0;
SR[M2:M0] = B’110;
SR[EM] = 1;
SR[GM] = 1;
PC = EVBA + 0x28;
AVR32
89

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