ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 272
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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21.9
21.9.1
21.9.2
8331A–AVR–07/11
Register Description – TWI Master
CTRLA
CTRLB
–
–
TWI Master Control Register A
TWI Master Control Register B
• Bit 7:6
These bits select the interrupt level for the TWI master interrupt, as described in
Programmable Multilevel Interrupt Controller” on page
• Bit 5
Setting the read interrupt enable (RIEN) bit enables the read interrupt when the read interrupt
flag (RIF) in the STATUS register is set. In addition the INTLVL bits must be nonzero for TWI
master interrupts to be generated.
• Bit 4
Setting the write interrupt enable (WIEN) bit enables the write interrupt when the write interrupt
flag (WIF) in the STATUS register is set. In addition the INTLVL bits must be nonzero for TWI
master interrupts to be generated.
• Bit 3
Setting the enable TWI master (ENABLE) bit enables the TWI master.
• Bit 2:0
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 7:4
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 3:2
Setting the inactive bus timeout (TIMEOUT) bits to a nonzero value will enable the inactive bus
timeout supervisor. If the bus is inactive for longer than the TIMEOUT setting, the bus state logic
will enter the idle state.
Table 21-3 on page 273
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
–
–
–
–
–
–
–
RIEN: Read Interrupt Enable
WIEN: Write Interrupt Enable
ENABLE: Enable TWI Master
INTLVL[1:0]: Interrupt Level
Reserved
Reserved
TIMEOUT[1:0]: Inactive Bus Timeout
R/W
7
0
7
–
R
0
INTLVL[1:0]
R/W
6
0
6
–
R
0
lists the timeout settings.
RIEN
R/W
R
5
0
5
–
0
WIEN
R/W
R
4
0
4
–
0
ENABLE
R/W
R/W
Atmel AVR XMEGA AU
3
0
3
0
TIMEOUT[1:0]
132.
R/W
R
2
–
0
2
0
QCEN
R/W
R
1
–
0
1
0
SMEN
R/W
R
”Interrupts and
0
–
0
0
0
CTRLA
CTRLB
272
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