ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 284
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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22. SPI – Serial Peripheral Interface
22.1
22.2
8331A–AVR–07/11
Features
Overview
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The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using
three or four pins. It allows fast communication between an XMEGA device and peripheral
devices or between several microcontrollers. The SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave.The master initiates and controls all
data transactions. The interconnection between master and slave devices with SPI is shown in
Figure 22-1 on page
tor. The SPI master initiates the communication cycle by pulling the slave select (SS) signal low
for the desired slave. Master and slave prepare the data to be sent in their respective shift regis-
ters, and the master generates the required clock pulses on the SCK line to interchange data.
Data are always shifted from master to slave on the master output, slave input (MOSI) line, and
from slave to master on the master input, slave output (MISO) line. After each data packet, the
master can synchronize the slave by pulling the SS line high.
Figure 22-1. SPI master-slave interconnection.
The SPI module is single buffered in the transmit direction and double buffered in the receive
direction. This means that bytes to be transmitted cannot be written to the SPI DATA register
before the entire shift cycle is completed. When receiving data, a received character must be
read from the DATA register before the next character has been completely shifted in. Other-
wise, the first byte will be lost.
In SPI slave mode, the control logic will sample the incoming signal on the SCK pin. To ensure
correct sampling of this clock signal, the minimum low and high periods must each be longer
than two CPU clock cycles.
Full-duplex, three-wire synchronous data transfer
Master or slave operation
Lsb first or msb first data transfer
Eight programmable bit rates
Interrupt flag at the end of transmission
Write collision flag to indicate data collision
Wake up from idle sleep mode
Double speed master mode
284. The system consists of two shift registers and a master clock genera-
Atmel AVR XMEGA AU
SHIFT
ENABLE
284
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