ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 87

• Manufacturer Part Number: ATxmega128A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A3U

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.7
8331A–AVR–07/11
DFLL 2MHz and DFLL 32MHz
Two built-in digital frequency locked loops (DFLLs) can be used to improve the accuracy of the
2MHz and 32MHz internal oscillators. The DFLL compares the oscillator frequency with a more
accurate reference clock to do automatic run-time calibration of the oscillator and compensate
for temperature and voltage drift. The choices for the reference clock sources are:
The DFLLs divide the oscillator reference clock by 32 to use a 1.024kHz reference. The refer-
ence clock is individually selected for each DFLL, as shown on
Figure 7-6.
The ideal counter value representing the frequency ratio between the internal oscillator and a
1.024kHz reference clock is loaded into the DFLL oscillator compare register (COMP) during
reset. For the 32MHz oscillator, this register can be written from software to make the oscillator
run at a different frequency or when the ratio between the reference clock and the oscillator is
different (for example when the USB start of frame is used). The 48MHz calibration values must
be read from the production signature row and written to the 32MHz CAL register before the
DFLL is enabled with USB SOF as reference source.
• 32.768kHz calibrated internal oscillator
• 32.768kHz crystal oscillator connected to the TOSC pins
• External clock
• USB start of frame
TOSC1
TOSC2
XTAL1
DFLL reference clock selection.
32.768 kHz Crystal Osc
32 MHz Int. RCOSC
32.768 kHz Int. Osc
2 MHz Int. RCOSC
External Clock
USB Start of Frame
DFLL32M
DFLL2M
clk
RC32MCREF
Atmel AVR XMEGA AU
XOSCSEL
DIV32
Figure 7-6 on page
DIV32
clk
RC2MCREF
87.
87