ATxmega128A4U Atmel Corporation, ATxmega128A4U Datasheet - Page 363

• Manufacturer Part Number: ATxmega128A4U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A4U

• Flash (kbytes): 128 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 34
• Ext Interrupts: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 7
• Twi (i2c): 2
• Uart: 5
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 5
• Output Compare Channels: 16
• Input Capture Channels: 16
• Pwm Channels: 16
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

28.9.6
8331A–AVR–07/11
Free running mode on two ADC channels with gain
Figure 28-17. ADC timing for single conversion on two ADC channels, CH1 with gain
Figure 28-18 on page 363
mode, CH0 and CH1 without gain and CH2 and CH3 with gain. When set up in free running
mode an ADC channel will continuously sample and do new conversions. In this example all
ADC channels are triggered at the same time, and each ADC channel sample and start convert-
ing as soon as the previous ADC channel is done with its sample and MSB conversion. After
four ADC clock cycles all ADC channels have done the first sample and started the first conver-
sion, and each ADC channels can then do the sample conversion start for their second
conversion. After 8 (for 12-bit mode) ADC clock cycles the first conversion is done for ADC
Channel 0, and the results for the rest of the ADC Channels is available in the next ADC clock
cycles. After the next clock cycle (in cycle 10) the result from the second ADC Channel is done
and available and so on. In this mode up to 8 conversions are ongoing at the same time.
Figure 28-18. ADC timing for free running mode
CONVERTING BIT CH0
CONVERTING BIT CH1
GAINSTAGE AMPLIFY
GAINSTAGE AMPLIFY
GAINSTAGE SAMPLE
START CH0, wo/GAIN
START CH1, wo/GAIN
START CH0, wo/GAIN
GAINSTAGE SAMPLE
START CH0, w/GAIN
START CH1, w/GAIN
START CH1, w/GAIN
CONV COMPLETE
ADC SAMPLE
ADC SAMPLE
CLK
CLK
IF CH0
IF CH1
ADC
ADC
1
1
0
shows the conversion timing for all four ADC channels in free running
2
2
MSB
10
2
1
3
3
MSB
2
9
10
3
2
8
4
4
3
7
9
3
6
8
5
5
Atmel AVR XMEGA AU
5
7
0
4
6
6
6
3
5
2
1
2
4
7
7
2
1
3
LSB
3
2
2
8
8
3
1
LSB
3
0
9
9
0
1
10
10
363